Add error on circular parameter definitions, bug329
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@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Accelerate bit-selected inversions.
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**** Add error on circular parameter definitions, bug329. [Alex Solomatnikov]
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**** Fix concatenates and vectored bufif1, bug326. [Iztok Jeras]
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* Verilator 3.811 2011/02/14
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@ -559,6 +559,8 @@ private:
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bool m_attrClockEn:1;// User clock enable attribute
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bool m_attrIsolateAssign:1;// User isolate_assignments attribute
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bool m_attrSFormat:1;// User sformat attribute
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bool m_didSigning:1; // V3Signed completed; can skip iteration
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bool m_didWidth:1; // V3Width completed; can skip iteration
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bool m_fileDescr:1; // File descriptor
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bool m_isConst:1; // Table contains constant data
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bool m_isStatic:1; // Static variable
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@ -572,6 +574,7 @@ private:
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m_sigPublic=false; m_sigModPublic=false; m_sigUserRdPublic=false; m_sigUserRWPublic=false;
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m_funcLocal=false; m_funcReturn=false;
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m_attrClockEn=false; m_attrIsolateAssign=false; m_attrSFormat=false;
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m_didSigning=false; m_didWidth=false;
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m_fileDescr=false; m_isConst=false; m_isStatic=false;
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m_trace=false;
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}
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@ -634,6 +637,10 @@ public:
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void attrScClocked(bool flag) { m_scClocked = flag; }
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void attrIsolateAssign(bool flag) { m_attrIsolateAssign = flag; }
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void attrSFormat(bool flag) { m_attrSFormat = flag; }
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void didSigning(bool flag) { m_didSigning=flag; }
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bool didSigning() const { return m_didSigning; }
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void didWidth(bool flag) { m_didWidth=flag; }
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bool didWidth() const { return m_didWidth; }
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void usedClock(bool flag) { m_usedClock = flag; }
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void usedParam(bool flag) { m_usedParam = flag; }
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void usedLoopIdx(bool flag) { m_usedLoopIdx = flag; }
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@ -149,6 +149,9 @@ private:
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// Inherit from others
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virtual void visit(AstVar* nodep, AstNUser*) {
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// Avoid recursion; can't use user() as they're all full, and anyhow this is often called
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if (nodep->didSigning()) return;
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nodep->didSigning(true);
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nodep->iterateChildren(*this);
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nodep->signedFrom(nodep->dtypep());
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}
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@ -528,7 +528,18 @@ private:
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//if (debug()) nodep->dumpTree(cout," InitPre: ");
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// Must have deterministic constant width
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// We can't skip this step when width()!=0, as creating a AstVar
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// with non-constant range gets size 1, not size 0.
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// with non-constant range gets size 1, not size 0. So use didWidth().
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if (nodep->didWidth()) { // Early exit if have circular parameter definition
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if (!nodep->width()) {
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if (!nodep->valuep()) nodep->v3fatalSrc("circular, but without value");
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nodep->v3error("Variable's initial value is circular: "<<nodep->prettyName());
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pushDeletep(nodep->valuep()->unlinkFrBack());
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nodep->valuep(new AstConst(nodep->fileline(), 1));
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} else {
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return;
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}
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}
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nodep->didWidth(true);
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int width=1; int mwidth=1;
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// Parameters if implicit untyped inherit from what they are assigned to
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AstBasicDType* bdtypep = nodep->dtypep()->castBasicDType();
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@ -0,0 +1,22 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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v_flags2 => ["--lint-only"],
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fails=>1,
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verilator_make_gcc => 0,
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make_top_shell => 0,
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make_main => 0,
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expect=>
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'%Error: t/t_param_circ_bad.v:\d+: Variable\'s initial value is circular: X
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%Error: Exiting due to.*',
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) if $Self->{v3};
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ok(1);
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1;
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@ -0,0 +1,12 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t (/*AUTOARG*/);
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sub sub ();
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endmodule
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module sub #(parameter WIDTH=X, parameter X=WIDTH)
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();
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endmodule
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