Split error tests from unsupported tests per review

test_regress/t/t_assert_seq_event_bad.out

@@ -0,0 +1,6 @@
+%Error: t/t_assert_seq_event_bad.v:19:7: Arguments to a sequence used as an event control must be static (IEEE 1800-2023 9.4.2.4)
+                                       : ... note: In instance 't'
+   19 |     @(s_arg(x));
+      |       ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to

test_regress/t/t_assert_seq_event_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(expect_filename=test.golden_filename, verilator_flags2=['--timing'], fails=True)
+
+test.passes()

test_regress/t/t_assert_seq_event_bad.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 PlanV GmbH
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+  input clk
+);
+
+  // verilog_format: off
+  sequence s_arg(x);
+    @(posedge clk) x;
+  endsequence
+  // verilog_format: on
+
+  task automatic f;
+    bit x = 1;
+    @(s_arg(x));
+  endtask
+
+  initial f();
+endmodule

test_regress/t/t_assert_seq_event_unsup.out

@@ -1,15 +1,6 @@
-%Error: t/t_assert_seq_event_unsup.v:25:7: Arguments to a sequence used as an event control must be static (IEEE 1800-2023 9.4.2.4)
+%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:18:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk)
-                                         : ... note: In instance 't'
-   25 |     @(s_arg(x));
-      |       ^~~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:15:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk)
                                                      : ... note: In instance 't'
-   15 |     @(g) a ##1 b;
+   18 |     @(g) a ##1 b;
       |     ^
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:29:6: Unsupported: Unclocked assertion
-                                                     : ... note: In instance 't'
-   29 |     @s_nonedge;
-      |      ^~~~~~~~~
 %Error: Exiting due to

test_regress/t/t_assert_seq_event_unsup.v

@@ -10,23 +10,16 @@ module t (
   bit a, b;
   logic g = 0;
 
+  default clocking @(posedge clk);
+  endclocking
+
   // verilog_format: off
   sequence s_nonedge;
     @(g) a ##1 b;
   endsequence
-
-  sequence s_arg(x);
-    @(posedge clk) x;
-  endsequence
   // verilog_format: on
 
-  task automatic f;
-    bit x = 1;
-    @(s_arg(x));
-  endtask
-
   initial begin
     @s_nonedge;
-    f();
   end
 endmodule

test_regress/t/t_sequence_ref_bad.out

@@ -0,0 +1,7 @@
+%Error: t/t_sequence_ref_bad.v:14:6: Concurrent assertion has no clock (IEEE 1800-2023 16.16)
+                                   : ... note: In instance 't'
+                                   : ... Suggest provide a clocking event, a default clocking, or a clocked procedural context
+   14 |     @s_one;
+      |      ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to

test_regress/t/t_sequence_ref_unsup.out

@@ -1,6 +0,0 @@
-%Error-UNSUPPORTED: t/t_sequence_ref_unsup.v:9:12: Unsupported: sequence referenced outside assertion property
-                                                 : ... note: In instance 't'
-    9 |   sequence s_one;
-      |            ^~~~~
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error: Exiting due to