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https://github.com/verilator/verilator.git
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Merge branch 'master' into develop-v5
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@@ -94,6 +94,7 @@ private:
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bool m_inDly = false; // True in delayed assignments
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bool m_inLoop = false; // True in for loops
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bool m_inInitial = false; // True in static initializers and initial blocks
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bool m_ignoreBlkAndNBlk = false; // Suppress delayed assignment BLKANDNBLK
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using VarMap = std::map<const std::pair<AstNodeModule*, std::string>, AstVar*>;
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VarMap m_modVarMap; // Table of new var names created under module
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VDouble0 m_statSharedSet; // Statistic tracking
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@@ -105,6 +106,7 @@ private:
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void markVarUsage(AstNodeVarRef* nodep, bool blocking) {
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// Ignore if warning is disabled on this reference (used by V3Force).
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if (nodep->fileline()->warnIsOff(V3ErrorCode::BLKANDNBLK)) return;
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if (m_ignoreBlkAndNBlk) return;
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if (blocking) nodep->user5(true);
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AstVarScope* const vscp = nodep->varScopep();
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// UINFO(4, " MVU " << blocking << " " << nodep << endl);
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@@ -517,6 +519,13 @@ private:
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}
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}
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virtual void visit(AstNodeReadWriteMem* nodep) override {
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VL_RESTORER(m_ignoreBlkAndNBlk);
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m_ignoreBlkAndNBlk = true; // $readmem/$writemem often used in mem models
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// so we will suppress BLKANDNBLK warnings
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iterateChildren(nodep);
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}
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virtual void visit(AstNodeFor* nodep) override { // LCOV_EXCL_LINE
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nodep->v3fatalSrc(
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"For statements should have been converted to while statements in V3Begin");
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