Fix no matching function calls for randomized `VlWide` in unpacked and dynamic arrays (#6290)

include/verilated_random.h

@@ -408,7 +408,7 @@ public:
 
     // Record a flat (non-class) element into the array variable table
     template <typename T>
-    typename std::enable_if<!std::is_class<T>::value, void>::type
+    typename std::enable_if<!std::is_class<T>::value || VlIsVlWide<T>::value, void>::type
     record_arr_table(T& var, const std::string& name, int dimension, std::vector<IData> indices,
                      std::vector<size_t> idxWidths) {
         const std::string key = generateKey(name, m_index);

test_regress/t/t_randomize_queue_wide.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if not test.have_solver:
+    test.skip("No constraint solver installed")
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_randomize_queue_wide.v

@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Foo;
+  rand bit [65:0] m_wideQueue[$];
+
+  function new;
+    m_wideQueue = '{3{0}};
+  endfunction
+
+  constraint int_queue_c {
+    m_wideQueue[0] == 0;
+    m_wideQueue[1] == 1;
+    m_wideQueue[2] == 2;
+  }
+  function void self_check();
+    if (m_wideQueue[0] != 0) $stop;
+    if (m_wideQueue[1] != 1) $stop;
+    if (m_wideQueue[2] != 2) $stop;
+  endfunction
+endclass
+
+module t;
+  int success;
+  initial begin
+    Foo foo = new;
+    success = foo.randomize();
+    if (success != 1) $stop;
+    foo.self_check();
+
+    $display("Queue: %p", foo.m_wideQueue);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule

test_regress/t/t_randomize_unpacked_wide.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if not test.have_solver:
+    test.skip("No constraint solver installed")
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_randomize_unpacked_wide.v

@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Foo;
+  rand bit [65:0] m_wideUnpacked[3];
+
+  constraint int_queue_c {
+    m_wideUnpacked[0] == 0;
+    m_wideUnpacked[1] == 1;
+    m_wideUnpacked[2] == 2;
+  }
+  function void self_check();
+    if (m_wideUnpacked[0] != 0) $stop;
+    if (m_wideUnpacked[1] != 1) $stop;
+    if (m_wideUnpacked[2] != 2) $stop;
+  endfunction
+endclass
+
+module t;
+  int success;
+  initial begin
+    Foo foo = new;
+    success = foo.randomize();
+    if (success != 1) $stop;
+    foo.self_check();
+
+    $display("Unpacked: %p", foo.m_wideUnpacked);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule