Tests: Fix assignment type mismatch (#6461)

test_regress/t/t_assert_elab_p.out

@@ -0,0 +1,4 @@
+-Info: t/t_assert_elab_p.v:14:5: %m test.sv:25: 4=4 2=2 STAGE_IDS='{'h1, 'h1, 'h1, 'h1}
+                               : ... note: In instance 't.pipe'
+   14 |     $info("%m %s:%0d: 4=%0d 2=%0d STAGE_IDS=%p", "test.sv", 25, 4, 2, STAGE_IDS);
+      |     ^~~~~

test_regress/t/t_assert_elab_p.py

@@ -11,6 +11,6 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile()
+test.compile(expect_filename=test.golden_filename)
 
 test.passes()

test_regress/t/t_assert_elab_p.v

@@ -18,15 +18,8 @@ endmodule
 module t #(
     parameter type ID_T = logic [4:0]
 );
-  function automatic ID_T [3:0][1:0] gen_stage_ids();
-    for (int unsigned st = 0; st < 4; st++) begin
-      for (int unsigned id = 0; id < 2; id++) begin
-        gen_stage_ids[st][id] = 3 + ((st + 1) * 2) + id - (3 + ((st + 1) * 2) + id < 18 ? 0 : 18);
-      end
-    end
-  endfunction
 
-  localparam ID_T STAGE_IDS[3:0][1:0] = gen_stage_ids();
+  localparam ID_T STAGE_IDS[3:0][1:0] = '{default: 5'b1};
 
   pipe_id_match #(
       .ID_T(ID_T),