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Add timescale directive for hier_block if the original design has it (#2554) 

* add timescale directive to a test to reproduce #2544

* add timescale directive to hierarchy blocks
This commit is contained in:
Yutetsu TAKATSUKASA 2020-09-17 06:09:29 +09:00 committed by GitHub
parent 430238a6b4
commit e48a859b86
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 22 additions and 8 deletions
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26
src/V3ProtectLib.cpp
View File

@ -82,7 +82,7 @@ private:
FileLine* fl = nodep->fileline(); FileLine* fl = nodep->fileline();
// Need to know the existence of clk before createSvFile() // Need to know the existence of clk before createSvFile()
m_hasClk = checkIfClockExists(nodep); m_hasClk = checkIfClockExists(nodep);
createSvFile(fl); createSvFile(fl, nodep);
createCppFile(fl); createCppFile(fl);
iterateChildren(nodep); iterateChildren(nodep);
@ -124,7 +124,7 @@ private:
addComment(txtp, fl, "Evaluates the secret module's final process"); addComment(txtp, fl, "Evaluates the secret module's final process");
} }
void createSvFile(FileLine* fl) { void createSvFile(FileLine* fl, AstNodeModule* modp) {
// Comments // Comments
AstTextBlock* txtp = new AstTextBlock(fl); AstTextBlock* txtp = new AstTextBlock(fl);
addComment(txtp, fl, "Wrapper module for DPI protected library"); addComment(txtp, fl, "Wrapper module for DPI protected library");
@ -135,18 +135,28 @@ private:
"See instructions in your simulator for how" "See instructions in your simulator for how"
" to use DPI libraries\n"); " to use DPI libraries\n");
bool timescaleShown = false;
if (v3Global.opt.hierChild() && !modp->timeunit().isNone()) {
// Emit timescale for hierarhical verilation
timescaleShown = true;
txtp->addText(fl, string("`timescale ") + modp->timeunit().ascii() + "/"
+ v3Global.rootp()->timeprecision().ascii() + "\n\n");
}
// Module declaration // Module declaration
m_modPortsp = new AstTextBlock(fl, "module " + m_libName + " (\n", false, true); m_modPortsp = new AstTextBlock(fl, "module " + m_libName + " (\n", false, true);
txtp->addNodep(m_modPortsp); txtp->addNodep(m_modPortsp);
txtp->addText(fl, ");\n\n"); txtp->addText(fl, ");\n\n");
// Timescale // Timescale
addComment(txtp, fl, if (!timescaleShown) {
"Precision of submodule" addComment(txtp, fl,
" (commented out to avoid requiring timescale on all modules)"); "Precision of submodule"
addComment(txtp, fl, string("timeunit ") + v3Global.rootp()->timeunit().ascii() + ";"); " (commented out to avoid requiring timescale on all modules)");
addComment(txtp, fl, addComment(txtp, fl, string("timeunit ") + v3Global.rootp()->timeunit().ascii() + ";");
string("timeprecision ") + v3Global.rootp()->timeprecision().ascii() + ";\n"); addComment(txtp, fl,
string("timeprecision ") + v3Global.rootp()->timeprecision().ascii()
+ ";\n");
}
// DPI declarations // DPI declarations
hashComment(txtp, fl); hashComment(txtp, fl);

4
test_regress/t/t_hier_block.v
View File

@ -9,6 +9,10 @@
`define HIER_BLOCK /*verilator hier_block*/ `define HIER_BLOCK /*verilator hier_block*/
`endif `endif
`ifndef PROTLIB_TOP
`timescale 1ns/1ps
`endif
interface byte_ifs(input clk); interface byte_ifs(input clk);
logic [7:0] data; logic [7:0] data;
modport sender(input clk, output data); modport sender(input clk, output data);