Verilog format

test_regress/t/t_constraint_dyn_array_reduction.v

@@ -19,7 +19,9 @@ module t;
   class XorTest;
     rand bit [7:0] data[];
     rand bit [7:0] result;
-    function new(); data = new[4]; endfunction
+    function new();
+      data = new[4];
+    endfunction
     constraint c_size {data.size() == 4;}
     constraint c_xor {result == data.xor();}
   endclass
@@ -27,7 +29,9 @@ module t;
   class SumTest;
     rand bit [7:0] data[];
     rand bit [7:0] result;
-    function new(); data = new[4]; endfunction
+    function new();
+      data = new[4];
+    endfunction
     constraint c_size {data.size() == 4;}
     constraint c_sum {result == data.sum();}
   endclass
@@ -35,7 +39,9 @@ module t;
   class AndTest;
     rand bit [7:0] data[];
     rand bit [7:0] result;
-    function new(); data = new[4]; endfunction
+    function new();
+      data = new[4];
+    endfunction
     constraint c_size {data.size() == 4;}
     constraint c_and {result == data.and();}
   endclass
@@ -43,7 +49,9 @@ module t;
   class OrTest;
     rand bit [7:0] data[];
     rand bit [7:0] result;
-    function new(); data = new[4]; endfunction
+    function new();
+      data = new[4];
+    endfunction
     constraint c_size {data.size() == 4;}
     constraint c_or {result == data.or();}
   endclass
@@ -51,7 +59,9 @@ module t;
   class ProductTest;
     rand bit [7:0] data[];
     rand bit [7:0] result;
-    function new(); data = new[4]; endfunction
+    function new();
+      data = new[4];
+    endfunction
     constraint c_size {data.size() == 4;}
     constraint c_prod {result == data.product();}
   endclass

test_regress/t/t_constraint_func_call_unsup.out

@@ -1,5 +1,5 @@
-%Warning-CONSTRAINTIGN: t/t_constraint_func_call_unsup.v:18:23: Unsupported: complex function in constraint, treating as state
+%Warning-CONSTRAINTIGN: t/t_constraint_func_call_unsup.v:16:22: Unsupported: complex function in constraint, treating as state
-   18 |   constraint c { x <= complex_func(y); }
+   16 |   constraint c {x <= complex_func(y);}
       |                      ^~~~~~~~~~~~
                         ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest
                         ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message.

test_regress/t/t_constraint_func_call_unsup.v

@@ -9,10 +9,8 @@ class Cls;
   rand bit [7:0] y;
 
   function bit [7:0] complex_func(bit [7:0] m);
-    if (m > 128)
+    if (m > 128) return m;
-      return m;
+    else return m + 1;
-    else
-      return m + 1;
   endfunction
 
   constraint c {x <= complex_func(y);}

test_regress/t/t_fork_dynscope_interface.v

@@ -29,7 +29,8 @@ interface Iface;
 endinterface
 
 module rvlab_tests (
-   Iface ifc);
+    Iface ifc
+);
   task test_idcode();
     bit [31:0] idcode_read;
     ifc.tsk(idcode_read, '0);

test_regress/t/t_fork_join_none_inactive.v

@@ -1,14 +1,17 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed under the Creative Commons Public Domain, for
+// This file ONLY is placed under the Creative Commons Public Domain.
-// any use, without warranty, 2026 by Antmicro Ltd.
+// SPDX-FileCopyrightText: 2026 Antmicro Ltd
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-    initial fork
+  initial
+  fork
     #0 $write("This should be last\n");
     begin
-            fork $write("This should be second\n"); join_none
+      fork
+        $write("This should be second\n");
+      join_none
       $write("This should be first\n");
     end
   join_none

test_regress/t/t_fork_join_none_nested_triggered.v

@@ -1,7 +1,7 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed under the Creative Commons Public Domain, for
+// This file ONLY is placed under the Creative Commons Public Domain.
-// any use, without warranty, 2026 by Antmicro Ltd.
+// SPDX-FileCopyrightText: 2026 Antmicro Ltd
 // SPDX-License-Identifier: CC0-1.0
 
 module test;

test_regress/t/t_fork_join_none_waiters.v

@@ -1,7 +1,7 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This file ONLY is placed under the Creative Commons Public Domain, for
+// This file ONLY is placed under the Creative Commons Public Domain.
-// any use, without warranty, 2026 by Antmicro Ltd.
+// SPDX-FileCopyrightText: 2026 Antmicro Ltd
 // SPDX-License-Identifier: CC0-1.0
 
 class events_holder;

test_regress/t/t_hier_block_import/t_hier_block_import_subsub.v

@@ -6,10 +6,10 @@
 // SPDX-FileCopyrightText: 2024 Antmicro
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-module subsub
+module subsub #(
-#(
     `include "t_hier_block_import.vh"
-)
+) (
-(output bit [31:0] out); /*verilator hier_block*/
+    output bit [31:0] out
+);  /*verilator hier_block*/
   assign out = pt.PARAM_VALUE;
 endmodule

test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v

@@ -6,12 +6,14 @@
 
 module detail_code (
     input clk,
-    input reset_l);
+    input reset_l
+);
 endmodule
 
 module sub_top (
     input clk,
-    input reset_l);
+    input reset_l
+);
 
   detail_code u0 (
       .clk(clk),

test_regress/t/t_interface_type_ref_internal.v

@@ -4,7 +4,11 @@
 // SPDX-FileCopyrightText: 2026 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-interface ifc #(parameter int width)(input logic [width-1:0] b);
+interface ifc #(
+    parameter int width
+) (
+    input logic [width-1:0] b
+);
   logic [width-1:0] a;
   typedef logic [width-1:0] type_t;
   always_comb a = type_t'(b);

test_regress/t/t_preproc_resolve.out

@@ -24,7 +24,8 @@ module submod(
   always_ff @(posedge clk or posedge rst) begin
     if (rst) begin
       out_signal <= 1'b0;
-      end else begin
+    end
+    else begin
       out_signal <= ~out_signal;
     end
   end

test_regress/t/t_preproc_resolve/submod.sv

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 `timescale 1ns / 1ps
-module submod(/*AUTOARG*/
+module submod (
     input logic clk,
     input logic rst,
     output logic out_signal
@@ -13,7 +13,8 @@ module submod(/*AUTOARG*/
   always_ff @(posedge clk or posedge rst) begin
     if (rst) begin
       out_signal <= 1'b0;
-      end else begin
+    end
+    else begin
       out_signal <= ~out_signal;
     end
   end

test_regress/t/t_randomize_this_inline.v

@@ -24,7 +24,10 @@ endclass
 class Caller;
   rand bit [7:0] own_value;
   function int do_rand(DataItem item);
-    return item.randomize() with { this.value > 8'd30; this.value < 8'd40; };
+    return item.randomize() with {
+      this.value > 8'd30;
+      this.value < 8'd40;
+    };
   endfunction
 endclass
 
@@ -35,18 +38,28 @@ module t;
     automatic int rand_ok;
 
     // Test 1: 'this.member' in inline constraint from module-level code
-    rand_ok = item.randomize() with { this.value > 8'd10; this.value < 8'd50; };
+    rand_ok = item.randomize() with {
+      this.value > 8'd10;
+      this.value < 8'd50;
+    };
     `checkd(rand_ok, 1)
     `check_range(item.value, 11, 49)
     `check_range(item.limit, 50, 200)
 
     // Test 2: multiple 'this.member' references
-    rand_ok = item.randomize() with { this.value > 8'd20; this.value < 8'd30; };
+    rand_ok = item.randomize() with {
+      this.value > 8'd20;
+      this.value < 8'd30;
+    };
     `checkd(rand_ok, 1)
     `check_range(item.value, 21, 29)
 
     // Test 3: mix of 'this.member' and unqualified member
-    rand_ok = item.randomize() with { this.value > 8'd5; this.value < 8'd100; limit > 8'd150; };
+    rand_ok = item.randomize() with {
+      this.value > 8'd5;
+      this.value < 8'd100;
+      limit > 8'd150;
+    };
     `checkd(rand_ok, 1)
     `check_range(item.value, 6, 99)
     `check_range(item.limit, 151, 200)