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Fix .vlt public_flat* and others to support long identifier names (#6516)

This commit is contained in:
Szymon Gizler 2025-09-30 22:55:11 +02:00 committed by GitHub
parent b902e4bcf5
commit e21c4fbbb5
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GPG Key ID: B5690EEEBB952194
5 changed files with 22 additions and 20 deletions
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4
src/V3Ast.h
View File

@ -585,8 +585,8 @@ public:
// ACCESSORS
virtual string name() const VL_MT_STABLE { return ""; }
virtual string origName() const { return ""; }
string prettyOrigOrName() const {
return prettyName(origName().empty() ? name() : origName());
string prettyDehashOrigOrName() const {
return prettyName(VName::dehash(origName().empty() ? name() : origName()));
}
virtual void name(const string& name) {
this->v3fatalSrc("name() called on object without name() method");

22
src/V3Control.cpp
View File

@ -263,7 +263,7 @@ public:
const VPragmaType pragma = VPragmaType::COVERAGE_BLOCK_OFF;
if (!nodep->unnamed()) {
for (const string& i : m_coverageOffBlocks) {
if (VString::wildmatch(nodep->prettyOrigOrName(), i)) {
if (VString::wildmatch(nodep->prettyDehashOrigOrName(), i)) {
nodep->addItemsp(new AstPragma{nodep->fileline(), pragma});
}
}
@ -274,7 +274,7 @@ public:
const VPragmaType pragma = VPragmaType::COVERAGE_BLOCK_OFF;
if (!nodep->unnamed()) {
for (const string& i : m_coverageOffBlocks) {
if (VString::wildmatch(nodep->prettyOrigOrName(), i)) {
if (VString::wildmatch(nodep->prettyDehashOrigOrName(), i)) {
nodep->addStmtsp(new AstPragma{nodep->fileline(), pragma});
}
}
@ -754,7 +754,7 @@ void V3Control::applyCoverageBlock(AstNodeModule* modulep, AstBegin* nodep) {
const string& filename = nodep->fileline()->filename();
V3ControlFile* const filep = V3ControlResolver::s().files().resolve(filename);
if (filep) filep->applyBlock(nodep);
const string& modname = modulep->prettyOrigOrName();
const string& modname = modulep->prettyDehashOrigOrName();
V3ControlModule* const modp = V3ControlResolver::s().modules().resolve(modname);
if (modp) modp->applyBlock(nodep);
}
@ -763,7 +763,7 @@ void V3Control::applyCoverageBlock(AstNodeModule* modulep, AstGenBlock* nodep) {
const string& filename = nodep->fileline()->filename();
V3ControlFile* const filep = V3ControlResolver::s().files().resolve(filename);
if (filep) filep->applyBlock(nodep);
const string& modname = modulep->prettyOrigOrName();
const string& modname = modulep->prettyDehashOrigOrName();
V3ControlModule* const modp = V3ControlResolver::s().modules().resolve(modname);
if (modp) modp->applyBlock(nodep);
}
@ -775,16 +775,16 @@ void V3Control::applyIgnores(FileLine* filelinep) {
}
void V3Control::applyModule(AstNodeModule* modulep) {
const string& modname = modulep->prettyOrigOrName();
const string& modname = modulep->prettyDehashOrigOrName();
V3ControlModule* const modp = V3ControlResolver::s().modules().resolve(modname);
if (modp) modp->apply(modulep);
}
void V3Control::applyFTask(AstNodeModule* modulep, AstNodeFTask* ftaskp) {
const string& modname = modulep->prettyOrigOrName();
const string& modname = modulep->prettyDehashOrigOrName();
V3ControlModule* const modp = V3ControlResolver::s().modules().resolve(modname);
if (!modp) return;
const V3ControlFTask* const ftp = modp->ftasks().resolve(ftaskp->prettyOrigOrName());
const V3ControlFTask* const ftp = modp->ftasks().resolve(ftaskp->prettyDehashOrigOrName());
if (ftp) ftp->apply(ftaskp);
}
@ -792,14 +792,14 @@ void V3Control::applyVarAttr(const AstNodeModule* modulep, const AstNodeFTask* f
AstVar* varp) {
V3ControlVar* vp;
V3ControlModule* const modp
= V3ControlResolver::s().modules().resolve(modulep->prettyOrigOrName());
= V3ControlResolver::s().modules().resolve(modulep->prettyDehashOrigOrName());
if (!modp) return;
if (ftaskp) {
V3ControlFTask* const ftp = modp->ftasks().resolve(ftaskp->prettyOrigOrName());
V3ControlFTask* const ftp = modp->ftasks().resolve(ftaskp->prettyDehashOrigOrName());
if (!ftp) return;
vp = ftp->vars().resolve(varp->prettyOrigOrName());
vp = ftp->vars().resolve(varp->prettyDehashOrigOrName());
} else {
vp = modp->vars().resolve(varp->prettyOrigOrName());
vp = modp->vars().resolve(varp->prettyDehashOrigOrName());
}
if (vp) vp->apply(varp);
}

3
test_regress/t/t_vpi_escape.cpp
View File

@ -156,7 +156,8 @@ int _mon_check_iter() {
TEST_CHECK_CSTR(p, "\\mod.with_dot ");
if (TestSimulator::is_verilator()) {
p = vpi_get_str(vpiDefName, vh2);
TEST_CHECK_CSTR(p, "sub");
TEST_CHECK_CSTR(
p, "sub_with_very___05Fvery_____VhshsmH6BYHIAHq4mnPF8T3lXnhhONMT1I4ouBvkJk58");
}
TestVpiHandle vh_null_name = my_vpi_handle("___0_");

12
test_regress/t/t_vpi_escape.v
View File

@ -62,13 +62,13 @@ extern "C" int mon_check();
integer status;
sub a0 (.cyc(cyc));
sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name a0 (.cyc(cyc));
sub \mod.with_dot (.cyc(cyc));
sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name \mod.with_dot (.cyc(cyc));
// Check if scope names are not decoded twice
sub ___0F_ (.cyc(cyc));
sub ___0_ (.cyc(cyc));
sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ___0F_ (.cyc(cyc));
sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ___0_ (.cyc(cyc));
initial begin
@ -112,12 +112,12 @@ extern "C" int mon_check();
endmodule
module sub (
module sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name (
input [31:0] cyc /*verilator public_flat_rd*/
);
reg \b.c /*verilator public_flat_rw*/;
reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/;
reg subsig2; // public in .vlt
`ifdef IVERILOG
// stop icarus optimizing signals away
wire redundant = subsig1 | subsig2 | \b.c ;

1
test_regress/t/t_vpi_escape.vlt
View File

@ -7,3 +7,4 @@
`verilator_config
public_flat_rd -module "*" -var "double__underscore__vlt"
public_flat_rd -module "sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name" -var "subsig2"