Fix -E duplicating output, bug1226.

Changes

@@ -33,6 +33,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix `` expansion of empty `defines, bug1225. [Odd Magne Reitan]
 
+****  Fix -E duplicating output, bug1226. [Odd Magne Reitan]
+
 
 * Verilator 3.912 2017-09-23
 

src/V3ParseImp.cpp

@@ -154,6 +154,8 @@ void V3ParseImp::parseFile(FileLine* fileline, const string& modfilename, bool i
     // Parse it
     if (!v3Global.opt.preprocOnly()) {
 	lexFile (modfilename);
+    } else {
+	m_ppBuffers.clear();
     }
 }
 
@@ -183,5 +185,5 @@ void V3Parse::parseFile(FileLine* fileline, const string& modname, bool inLibrar
     m_impp->parseFile(fileline, modname, inLibrary, errmsg);
 }
 void V3Parse::ppPushText(V3ParseImp* impp, const string& text) {
-    impp->ppPushText(text);
+    if (text != "") impp->ppPushText(text);
 }

test_regress/t/t_preproc_persist.out

@@ -0,0 +1,3 @@
+Inside "t/t_preproc_persist.v".
+Inside "t/t_preproc_persist_inc.v".
+Inside "t/t_preproc_persist2.v".

test_regress/t/t_preproc_persist.pl

@@ -0,0 +1,28 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp";
+
+compile (
+    # Override default flags
+    v_flags => [''],
+    v_other_filenames => ["t_preproc_persist2.v"],
+    verilator_flags => ["-E -P +incdir+t"],
+    verilator_flags2 => ['',],
+    verilator_flags3 => ['',],
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    stdout_filename => $stdout_filename,
+    );
+
+ok(files_identical($stdout_filename, "t/$Self->{name}.out"));
+
+1;

test_regress/t/t_preproc_persist.v

@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+Inside `__FILE__.
+
+`include "t_preproc_persist_inc.v"

test_regress/t/t_preproc_persist2.v

@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+Inside `__FILE__.
+
+`include "t_preproc_persist_inc.v"

test_regress/t/t_preproc_persist_inc.v

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+
+`ifndef COMMON_GUARD
+ `define COMMON_GUARD 1
+Inside `__FILE__.
+`endif
+