Support inside expressions with strings and doubles (#4138) (#4139)

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Krzysztof Boroński 2023-05-11 02:36:41 +02:00 committed by GitHub
parent d5de67c6dc
commit e095bf1af0
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3 changed files with 82 additions and 12 deletions

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@ -2473,23 +2473,35 @@ private:
nextip = itemp->nextp(); // iterate may cause the node to get replaced
VL_DO_DANGLING(userIterate(itemp, WidthVP{CONTEXT_DET, PRELIM}.p()), itemp);
}
// Take width as maximum across all items
int width = nodep->exprp()->width();
int mwidth = nodep->exprp()->widthMin();
for (const AstNode* itemp = nodep->itemsp(); itemp; itemp = itemp->nextp()) {
width = std::max(width, itemp->width());
mwidth = std::max(mwidth, itemp->widthMin());
AstBasicDType* dtype = VN_CAST(nodep->exprp()->dtypep(), BasicDType);
AstNodeDType* subDTypep = nullptr;
if (dtype && dtype->isString()) {
nodep->dtypeSetString();
subDTypep = nodep->findStringDType();
} else if (dtype && dtype->isDouble()) {
nodep->dtypeSetDouble();
subDTypep = nodep->findDoubleDType();
} else {
// Take width as maximum across all items
int width = nodep->exprp()->width();
int mwidth = nodep->exprp()->widthMin();
for (const AstNode* itemp = nodep->itemsp(); itemp; itemp = itemp->nextp()) {
width = std::max(width, itemp->width());
mwidth = std::max(mwidth, itemp->widthMin());
}
nodep->dtypeSetBit();
subDTypep = nodep->findLogicDType(width, mwidth, nodep->exprp()->dtypep()->numeric());
}
// Apply width
AstNodeDType* const subDTypep
= nodep->findLogicDType(width, mwidth, nodep->exprp()->dtypep()->numeric());
iterateCheck(nodep, "Inside expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep,
EXTEND_EXP);
for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
nextip = itemp->nextp(); // iterate may cause the node to get replaced
iterateCheck(nodep, "Inside Item", itemp, CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP);
}
nodep->dtypeSetBit();
if (debug() >= 9) nodep->dumpTree("- inside-in: ");
// Now rip out the inside and replace with simple math
AstNodeExpr* newp = nullptr;
@ -2513,8 +2525,8 @@ private:
"Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13)");
continue;
} else {
inewp = new AstEqWild{itemp->fileline(), nodep->exprp()->cloneTree(true),
itemp->unlinkFrBack()};
inewp = AstEqWild::newTyped(itemp->fileline(), nodep->exprp()->cloneTree(true),
itemp->unlinkFrBack());
}
if (newp) {
newp = new AstOr{nodep->fileline(), newp, inewp};

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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

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@ -0,0 +1,37 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
function bit check_string(string s);
if (s inside {"RW", "WO"})
return 1'b1;
return 1'b0;
endfunction
function bit check_double(real d);
if (d inside {0.0, 2.5})
return 1'b1;
return 1'b0;
endfunction
module t();
initial begin
if (!check_string("WO"))
$stop;
if (!check_string("RW"))
$stop;
if (check_string("ABC"))
$stop;
if (!check_double(0.0))
$stop;
if (!check_double(2.5))
$stop;
if (check_double(1.0))
$stop;
$display("*-* All Finished *-*");
$finish;
end
endmodule