parent
d5de67c6dc
commit
e095bf1af0
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@ -2473,23 +2473,35 @@ private:
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nextip = itemp->nextp(); // iterate may cause the node to get replaced
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VL_DO_DANGLING(userIterate(itemp, WidthVP{CONTEXT_DET, PRELIM}.p()), itemp);
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}
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// Take width as maximum across all items
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int width = nodep->exprp()->width();
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int mwidth = nodep->exprp()->widthMin();
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for (const AstNode* itemp = nodep->itemsp(); itemp; itemp = itemp->nextp()) {
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width = std::max(width, itemp->width());
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mwidth = std::max(mwidth, itemp->widthMin());
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AstBasicDType* dtype = VN_CAST(nodep->exprp()->dtypep(), BasicDType);
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AstNodeDType* subDTypep = nullptr;
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if (dtype && dtype->isString()) {
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nodep->dtypeSetString();
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subDTypep = nodep->findStringDType();
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} else if (dtype && dtype->isDouble()) {
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nodep->dtypeSetDouble();
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subDTypep = nodep->findDoubleDType();
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} else {
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// Take width as maximum across all items
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int width = nodep->exprp()->width();
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int mwidth = nodep->exprp()->widthMin();
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for (const AstNode* itemp = nodep->itemsp(); itemp; itemp = itemp->nextp()) {
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width = std::max(width, itemp->width());
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mwidth = std::max(mwidth, itemp->widthMin());
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}
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nodep->dtypeSetBit();
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subDTypep = nodep->findLogicDType(width, mwidth, nodep->exprp()->dtypep()->numeric());
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}
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// Apply width
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AstNodeDType* const subDTypep
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= nodep->findLogicDType(width, mwidth, nodep->exprp()->dtypep()->numeric());
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iterateCheck(nodep, "Inside expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep,
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EXTEND_EXP);
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for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
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nextip = itemp->nextp(); // iterate may cause the node to get replaced
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iterateCheck(nodep, "Inside Item", itemp, CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP);
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}
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nodep->dtypeSetBit();
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if (debug() >= 9) nodep->dumpTree("- inside-in: ");
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// Now rip out the inside and replace with simple math
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AstNodeExpr* newp = nullptr;
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@ -2513,8 +2525,8 @@ private:
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"Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13)");
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continue;
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} else {
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inewp = new AstEqWild{itemp->fileline(), nodep->exprp()->cloneTree(true),
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itemp->unlinkFrBack()};
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inewp = AstEqWild::newTyped(itemp->fileline(), nodep->exprp()->cloneTree(true),
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itemp->unlinkFrBack());
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}
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if (newp) {
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newp = new AstOr{nodep->fileline(), newp, inewp};
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@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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@ -0,0 +1,37 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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function bit check_string(string s);
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if (s inside {"RW", "WO"})
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return 1'b1;
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return 1'b0;
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endfunction
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function bit check_double(real d);
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if (d inside {0.0, 2.5})
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return 1'b1;
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return 1'b0;
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endfunction
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module t();
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initial begin
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if (!check_string("WO"))
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$stop;
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if (!check_string("RW"))
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$stop;
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if (check_string("ABC"))
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$stop;
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if (!check_double(0.0))
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$stop;
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if (!check_double(2.5))
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$stop;
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if (check_double(1.0))
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$stop;
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$display("*-* All Finished *-*");
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$finish;
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end
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endmodule
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Loading…
Reference in New Issue