Fix tracing with `--main-top-name -` (#5261).

Changes

@@ -30,6 +30,7 @@ Verilator 5.027 devel
 * Fix error on empty generate with -O0 (#5250).
 * Fix unconstrained randomization of unpacked structs (#5252). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix inlining of variables driven from forced vars (#5259). [Geza Lore]
+* Fix tracing with `--main-top-name -` (#5261). [Ethan Sifferman]
 
 
 Verilator 5.026 2024-06-15

src/V3EmitCModel.cpp

@@ -551,11 +551,11 @@ class EmitCModel final : public EmitCFunc {
              "0.\");\n");
         puts("}\n");
         puts("vlSymsp->__Vm_baseCode = code;\n");
-        puts("tracep->pushPrefix(std::string{vlSymsp->name()}, "
+        puts("if (strlen(vlSymsp->name())) tracep->pushPrefix(std::string{vlSymsp->name()}, "
              "VerilatedTracePrefixType::SCOPE_MODULE);\n");
         puts(topModNameProtected + "__" + protect("trace_decl_types") + "(tracep);\n");
         puts(topModNameProtected + "__" + protect("trace_init_top") + "(vlSelf, tracep);\n");
-        puts("tracep->popPrefix();\n");
+        puts("if (strlen(vlSymsp->name())) tracep->popPrefix();\n");
         puts("}\n");
 
         // Forward declaration

test_regress/t/t_trace_no_top_name.out

@@ -0,0 +1,13 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module another_top $end
+  $var wire 1 # b $end
+ $upscope $end
+ $scope module t $end
+  $var wire 1 # a $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#

test_regress/t/t_trace_no_top_name.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--binary --main-top-name '-' --trace -Wno-MULTITOP"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+vcd_identical($Self->trace_filename, $Self->{golden_filename});
+
+ok(1);
+1;

test_regress/t/t_trace_no_top_name.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t;
+   wire a = 0;
+   initial begin
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+      $dumpvars;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module another_top;
+   wire b = 0;
+endmodule