Add ASSIGNIN as suppressable error.

Changes

@@ -8,8 +8,9 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Fix "always @ (* )", bug403, bug404.  [Walter Lavino]
 
-**** Fix 3.823 constructor core dump on Debian, bug401.  [Ahmed El-Mahmoudy]
+***  Add ASSIGNIN as suppressable error.  [Jeremy Bennett]
 
+**** Fix 3.823 constructor core dump on Debian, bug401.  [Ahmed El-Mahmoudy]
 
 * Verilator 3.823 2011/10/20
 

bin/verilator

@@ -2377,6 +2377,17 @@ List of all warnings:
 
 =over 4
 
+=item ASSIGNIN
+
+Error that an assignment is being made to an input signal.  This is almost
+certainly a mistake, though technically legal.
+
+    input a;
+    assign a = 1'b1;
+
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item ASSIGNDLY
 
 Warns that you have an assignment statement with a delayed time in front of

src/V3Error.h

@@ -48,14 +48,15 @@ public:
 	I_LINT,		// All lint messages
 	I_DEF_NETTYPE_WIRE,  // `default_nettype is WIRE (false=NONE)
 	// Error codes:
+	E_BLKLOOPINIT,	// Error: Delayed assignment to array inside for loops
 	E_MULTITOP,	// Error: Multiple top level modules
 	E_TASKNSVAR,	// Error: Task I/O not simple
-	E_BLKLOOPINIT,	// Error: Delayed assignment to array inside for loops
 	//
 	// Warning codes:
 	EC_FIRST_WARN,	// Just a code so the program knows where to start warnings
 	//
 	ASSIGNDLY,	// Assignment delays
+	ASSIGNIN,	// Assigning to input
 	BLKANDNBLK,	// Blocked and non-blocking assignments to same variable
 	BLKSEQ,		// Blocking assignments in sequential block
 	CASEINCOMPLETE,	// Case statement has missing values
@@ -105,10 +106,10 @@ public:
 	    // Boolean
 	    " I_COVERAGE", " I_TRACING", " I_LINT", " I_DEF_NETTYPE_WIRE",
 	    // Errors
-	    "MULTITOP", "TASKNSVAR", "BLKLOOPINIT",
+	    "BLKLOOPINIT", "MULTITOP", "TASKNSVAR",
 	    // Warnings
 	    " EC_FIRST_WARN",
-	    "ASSIGNDLY",
+	    "ASSIGNDLY", "ASSIGNIN",
 	    "BLKANDNBLK", "BLKSEQ",
 	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CDCRSTLOGIC", "CMPCONST",
 	    "COMBDLY", "DEFPARAM", "DECLFILENAME",
@@ -130,7 +131,8 @@ public:
     bool dangerous() const { return ( m_e==COMBDLY ); }
     // Warnings we'll present to the user as errors
     // Later -Werror- options may make more of these.
-    bool pretendError() const { return ( m_e==BLKANDNBLK || m_e==IMPURE || m_e==MODDUP || m_e==SYMRSVDWORD); }
+    bool pretendError() const { return ( m_e==ASSIGNIN || m_e==BLKANDNBLK
+					 || m_e==IMPURE || m_e==MODDUP || m_e==SYMRSVDWORD); }
     // Warnings to mention manual
     bool mentionManual() const { return ( m_e==EC_FATALSRC || pretendError() ); }
 

src/V3LinkLValue.cpp

@@ -65,7 +65,7 @@ private:
 	if (nodep->varp()) {
 	    if (nodep->lvalue() && nodep->varp()->isInOnly()) {
 		if (!m_ftaskp) {
-		    nodep->v3error("Assigning to input variable: "<<nodep->prettyName());
+		    nodep->v3warn(ASSIGNIN,"Assigning to input variable: "<<nodep->prettyName());
 		}
 	    }
 	    if (nodep->lvalue() && nodep->varp()->isConst()

test_regress/t/t_var_in_assign.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_var_in_assign.v

@@ -0,0 +1,64 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   integer	v;
+
+   reg 	i;
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire			oa;			// From a of a.v
+   wire			oz;			// From z of z.v
+   // End of automatics
+
+   a a (.*);
+   z z (.*);
+
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
+`endif
+      cyc <= cyc + 1;
+      i <= cyc[0];
+      if (cyc==0) begin
+	 v = 3;
+	 if (v !== 3) $stop;
+	 if (assignin(v) !== 2) $stop;
+	 if (v !== 3) $stop; // Make sure V didn't get changed
+      end
+      else if (cyc<10) begin
+	 if (cyc==11 && oz!==1'b0)  $stop;
+	 if (cyc==12 && oz!==1'b1)  $stop;
+	 if (cyc==12 && oa!==1'b1)  $stop;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+   function integer assignin(input integer i);
+      i = 2;
+      assignin = i;
+   endfunction 
+
+endmodule
+
+module a (input i, output oa);
+   // verilator lint_off ASSIGNIN
+   assign i = 1'b1;
+   assign oa = i;
+endmodule
+
+module z (input i, output oz);
+   assign oz = i;
+endmodule

test_regress/t/t_var_in_assign_bad.pl

@@ -13,8 +13,8 @@ compile (
 	 v_flags2 => ["--lint-only --Mdir obj_lint_only"],
 	 fails=>1,
 	 expect=>
-'%Error: t/t_var_in_assign_bad.v:\d+: Assigning to input variable: value
-%Error: t/t_var_in_assign_bad.v:\d+: Assigning to input variable: valueSub
+'%Error-ASSIGNIN: t/t_var_in_assign_bad.v:\d+: Assigning to input variable: value
+%Error-ASSIGNIN: t/t_var_in_assign_bad.v:\d+: Assigning to input variable: valueSub
 %Error: Exiting due to.*',
     );