Fix always_ff on constant (#6519)

src/V3DfgOptimizer.cpp

@@ -266,6 +266,11 @@ class DataflowOptimize final {
                     if (hasExtWr) DfgVertexVar::setHasExtWrRefs(vscp);
                     return;
                 }
+                // TODO: remove once Actives can tolerate NEVER SenItems
+                if (AstSenItem* senItemp = VN_CAST(nodep, SenItem)) {
+                    senItemp->foreach(
+                        [](AstVarRef* refp) { DfgVertexVar::setHasExtRdRefs(refp->varScopep()); });
+                }
             } else {
                 if (AstVar* const varp = VN_CAST(nodep, Var)) {
                     const bool hasExtRd = varp->isPrimaryIO() || varp->isSigUserRdPublic()  //

test_regress/t/t_always_ff_never.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_always_ff_never.v

@@ -0,0 +1,40 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface intf
+    (input wire clk /*verilator public*/ );
+endinterface
+
+module sub (
+    input wire clk,
+    input wire dat
+);
+    intf the_intf (.clk);
+
+    logic [63:0] last_transition = 123;
+    always_ff @(edge dat) begin
+        last_transition <= $time;
+    end
+
+    int cyc = 0;
+    always_ff @(posedge clk) begin
+        cyc <= cyc + 1;
+        if (cyc == 2) begin
+            if (last_transition != 123) $stop;
+            $write("*-* All Finished *-*\n");
+            $finish;
+        end
+    end
+endmodule
+
+module t (/*AUTOARG*/
+          // Inputs
+          clk
+          );
+   input clk;
+
+    sub the_sub (.clk, .dat ('0));
+endmodule