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Fix signed wildcard comparisons.

This commit is contained in:
Wilson Snyder 2019-11-16 09:58:01 -05:00
parent b1c14e485a
commit de7caad710
2 changed files with 14 additions and 0 deletions
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2
src/V3Width.cpp
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@ -3692,6 +3692,8 @@ private:
case AstType::atNeq: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atEqCase: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atNeqCase: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atEqWild: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atNeqWild: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atAdd: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atSub: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;
case AstType::atShiftL: nodep->dtypeChgSigned(signedFlavorNeeded); return NULL;

12
test_regress/t/t_math_eq.v
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@ -77,4 +77,16 @@ module Test (/*AUTOARG*/
assign out[1] = in[3:0] !=? 4'b1001;
assign out[2] = in[3:0] ==? 4'bx01x;
assign out[3] = in[3:0] !=? 4'bx01x;
wire signed [3:0] ins = in[3:0];
wire signed [3:0] outs;
assign outs[0] = ins ==? 4'sb1001;
assign outs[1] = ins !=? 4'sb1001;
assign outs[2] = ins ==? 4'sbx01x;
assign outs[3] = ins !=? 4'sbx01x;
always_comb if (out != outs) $stop;
endmodule