Improve error that assert-under-assert is unsupported
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@ -89,7 +89,9 @@ private:
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}
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}
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}
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}
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void visit(AstNodeCoverOrAssert* nodep) override {
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void visit(AstNodeCoverOrAssert* nodep) override {
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if (m_assertp) nodep->v3error("Assert not allowed under another assert");
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if (m_assertp) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: Assert not allowed under another assert");
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}
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m_assertp = nodep;
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m_assertp = nodep;
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iterateChildren(nodep);
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iterateChildren(nodep);
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m_assertp = nullptr;
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m_assertp = nullptr;
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@ -0,0 +1,5 @@
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%Error-UNSUPPORTED: t/t_cover_assert.v:42:16: Unsupported: Assert not allowed under another assert
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42 | A2: assert (b);
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| ^~~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: Exiting due to
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@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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lint(
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verilator_flags2 => ["-Wall -Wno-DECLFILENAME --coverage"],
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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@ -0,0 +1,46 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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bit a;
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bit b;
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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a <= '0;
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b <= '0;
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end
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else if (cyc == 10) begin
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a <= '1;
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b <= '1;
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end
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else if (cyc == 11) begin
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a <= '0;
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b <= '1;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always_ff @(posedge clk) begin
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C1: cover property(a)
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begin
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// Assert under cover legal in some other simulators
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A2: assert (b);
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end
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end
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endmodule
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@ -37,7 +37,6 @@ foreach my $s (
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'/*verilator sformat*/ can only be applied to last argument of ',
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'/*verilator sformat*/ can only be applied to last argument of ',
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'Argument needed for string.',
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'Argument needed for string.',
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'Array initialization has too few elements, need element ',
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'Array initialization has too few elements, need element ',
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'Assert not allowed under another assert',
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'Assigned pin is neither input nor output',
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'Assigned pin is neither input nor output',
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'Assignment pattern with no members',
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'Assignment pattern with no members',
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'Attempted parameter setting of non-parameter: Param ',
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'Attempted parameter setting of non-parameter: Param ',
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