luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[#73220] add better logging in SAIF objects comparison

This commit is contained in:
Mateusz Gancarz 2025-02-21 11:08:45 +01:00
parent 3ffee61df9
commit dd78eda343
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
test_regress/driver.py
View File

@ -2484,14 +2484,14 @@ class VlTest:
other_signal = second.nets[signal_name]
if other_signal.width != signal.width:
self.error(f"Incompatible signal width in {signal_name}!\n")
self.error(f"Incompatible signal width in {signal_name} {signal.width} != {other_signal.width}\n")
for bit_index in range(signal.width):
signal_bit = signal.bits[bit_index]
other_signal_bit = other_signal.bits[bit_index]
if signal_bit.high_time != other_signal_bit.high_time or signal_bit.low_time != other_signal_bit.low_time or signal_bit.transitions != other_signal_bit.transitions:
self.error(f"Incompatible signal bit parameters in {signal_name}[{bit_index}]!\n")
self.error(f"Incompatible signal bit parameters in {signal_name}[{bit_index}]\n")
for instance_name, instance in first.child_instances.items():
if instance_name not in second.child_instances: