Apply 'make format'

src/V3Const.cpp

@@ -2792,11 +2792,11 @@ class ConstVisitor final : public VNVisitor {
     // required (m_required=true), call replaceWithSimulation() to compute
     // the slice via simulation.  Otherwise just iterate the children.
     void visit(AstSliceSel* nodep) override {
-       // First constify or width any child nodes
+        // First constify or width any child nodes
-       iterateChildren(nodep);
+        iterateChildren(nodep);
-       if (!m_required) return;  // Do nothing unless we are in parameter mode
+        if (!m_required) return;  // Do nothing unless we are in parameter mode
-       // Fallback to simulation: this will invoke SimulateVisitor::visit(AstSliceSel*)
+        // Fallback to simulation: this will invoke SimulateVisitor::visit(AstSliceSel*)
-       replaceWithSimulation(nodep);
+        replaceWithSimulation(nodep);
     }
 
     void visit(AstCAwait* nodep) override {

src/V3Param.cpp

@@ -737,8 +737,8 @@ class ParamProcessor final {
                 // integer array and include it in the module name.  Constantify nested
                 // expressions before mangling the value number.
                 V3Const::constifyParamsEdit(pinp->exprp());
-                longnamer += "_" + paramSmallName(srcModp, modvarp)
+                longnamer
-                    + paramValueNumber(pinp->exprp());
+                    += "_" + paramSmallName(srcModp, modvarp) + paramValueNumber(pinp->exprp());
                 any_overridesr = true;
             } else {
                 V3Const::constifyParamsEdit(pinp->exprp());

test_regress/t/t_param_slice.py

@@ -10,7 +10,7 @@ import vltest_bootstrap
 
 test.scenarios('vlt')
 
-test.compile(verilator_flags2=['--exe','--main','--timing'])
+test.compile(verilator_flags2=['--exe', '--main', '--timing'])
 
 test.execute()