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Tests: SHow expected values in t_typenames

This commit is contained in:
Wilson Snyder 2024-05-30 22:54:40 -04:00
parent 53c2e416f4
commit dbf68a99e8
2 changed files with 41 additions and 37 deletions
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35
test_regress/t/t_typename.out
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@ -1,19 +1,20 @@
real "real" ==? "real"
int "bit" ==? "bit"
int "int" ==? "int"
logic "logic" ==? "logic"
string "string" ==? "string"
real "real" ==? "real"
logic "logic" ==? "logic"
bit "bit" ==? "bit"
bit[2:0] "bit[2:0]" ==? "bit[2:0]"
bit$[3:2] "bit$[3:2]" ==? "bit$[3:2]"
bit$[3:1][4:5] "bit$[3:1][4:5]" ==? "bit$[3:1][4:5]"
bit "bit" ==? "bit"
bit[2:0] "bit[2:0]" ==? "bit[2:0]"
int "int" ==? "int"
A::__typeimpenum1 "bit[9:1]" ==? "bit[9:1]"
bit[9:1] "A::__typeimpenum1" ==? "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::<unspecified>"
STRUCTDTYPE 't.AB_t'$[0:9] "STRUCTDTYPE 't.AB_t'" ==? "struct{bit A;bit B;}"
"STRUCTDTYPE 't.AB_t'$[0:9]" ==? "struct{bit A;bit B;}top.AB_t$[0:9]"
*-* All Finished *-* *-* All Finished *-*

43
test_regress/t/t_typename.v
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@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
`define printtype(mytype) $write({$typename(mytype), "\n"}); `define printtype(mytype, expec) $write({"\"", $typename(mytype), "\" ==? \"", expec, "\"\n"});
// Copied from 20.6.1 Type name function in IEEE 1800-2017 // Copied from 20.6.1 Type name function in IEEE 1800-2017
// source code // $typename would return // source code // $typename would return
@ -35,33 +35,36 @@ module t(/*AUTOARG*/);
mybit_t bitu32 [3:2]; mybit_t bitu32 [3:2];
mybit_t bitu31 [3:1][4:5]; mybit_t bitu31 [3:1][4:5];
// From LRM
// from LRM
typedef struct {node A,B;} AB_t; typedef struct {node A,B;} AB_t;
AB_t AB[10]; // "struct{bit A;bit B;}top.AB_t$[0:9]" AB_t AB[10]; // "struct{bit A;bit B;}top.AB_t$[0:9]"
initial begin initial begin
// $write({$typename(real), "\n"}); // $write({$typename(real), "\n"});
`printtype(real); `printtype(real, "real");
`printtype(int); `printtype(bit, "bit");
`printtype(int); `printtype(int, "int");
`printtype(logic); `printtype(logic, "logic");
`printtype(string); `printtype(string, "string");
`printtype(r); `printtype(r, "real");
`printtype(l); `printtype(l, "logic");
`printtype(mybit_t); `printtype(mybit_t, "bit");
`printtype(bitp20); `printtype(bitp20, "bit[2:0]");
`printtype(bitu32); `printtype(bitu32, "bit$[3:2]");
`printtype(bitu31); `printtype(bitu31, "bit$[3:1][4:5]");
$write("\n"); $write("\n");
// from LRM // from LRM
`printtype(node); // bit `printtype(node, "bit");
`printtype(X); // bit [2:0] `printtype(X, "bit[2:0]");
`printtype(Y); // int `printtype(Y, "int");
`printtype(A::X); // enum{A=32'sd0,B=32'sd1,C=32'sd99}A::e$1
`printtype(A::word); // A::bit[9:1] `printtype(A::word, "bit[9:1]");
`printtype(AB); // struct{bit A;bit B;}top.AB_t$[0:9]
`printtype(A::X, "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::<unspecified>");
`printtype(AB_t, "struct{bit A;bit B;}");
`printtype(AB, "struct{bit A;bit B;}top.AB_t$[0:9]");
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;