Add error on function invoking time-controlling statements (#6385).

Changes

@@ -16,12 +16,12 @@ Verilator 5.041 devel
 * Add error on parameter values from hierarchical paths (#1626) (#6456). [Luca Rufer]
 * Add error on zero/negative unpacked dimensions (#1642). [Stefan Wallentowitz]
 * Add verilator_gantt profiling of DPI imports (#3084). [Geza Lore]
+* Add ASSIGNEQEXPR when use `=` inside expressions (#5567). [Ethan Sifferman]
 * Add error on non-packed struct randc (#5999). [Seth Pellegrino]
 * Add configure `--enable-asan` to compile verilator_bin with the address sanitizer (#6404). [Geza Lore]
 * Add $(LDFLAGS) and $(LIBS) to when building shared libraries (#6425) (#6426). [Ahmed El-Mahmoudy]
-* Add ASSIGNEQEXPR when use `=` inside expressions (#5567). [Ethan Sifferman]
 * Add IMPLICITSTATIC also on procedure variables.
-* Add error on function invoking task.
+* Add error on function invoking task or time-controlling statements (#6385).
 * Deprecate sensitivity list on public_flat_rw attributes (#6443). [Geza Lore]
 * Deprecate clocker attribute and --clk option (#6463). [Geza Lore]
 * Support modports referencing clocking blocks (#4555) (#6436). [Ryszard Rozak, Antmicro Ltd.]

src/V3WidthCommit.cpp

@@ -64,8 +64,15 @@ public:
 private:
     // METHODS
     void editDType(AstNode* nodep) {
-        // Edit dtypes for this node
+        // Called by every visitor. Edit dtypes for this node, also check for some warnings
         nodep->dtypep(editOneDType(nodep->dtypep()));
+        if (m_ftaskp && m_ftaskp->verilogFunction() && m_taskRefWarn && nodep->isTimingControl())
+            nodep->v3error(
+                "Functions cannot contain time-controlling statements (IEEE 1800-2023 13.4)\n"
+                << nodep->warnContextPrimary() << "\n"
+                << nodep->warnMore() << "... Suggest make caller 'function "
+                << m_ftaskp->prettyName() << "' a task\n"
+                << m_ftaskp->warnContextSecondary());
     }
     AstNodeDType* editOneDType(AstNodeDType* nodep) {
         // See if the dtype/refDType can be converted to a standard one
@@ -221,7 +228,7 @@ private:
     void visit(AstFork* nodep) override {
         VL_RESTORER(m_taskRefWarn);
         // fork..join_any is allowed to call tasks, and UVM does this
-        if (nodep->joinType().joinNone()) m_taskRefWarn = false;
+        if (!nodep->isTimingControl()) m_taskRefWarn = false;
         iterateChildren(nodep);
         editDType(nodep);
     }

test_regress/t/t_func_bad_time.out

@@ -0,0 +1,16 @@
+%Error: t/t_func_bad_time.v:12:5: Functions cannot contain time-controlling statements (IEEE 1800-2023 13.4)
+                                : ... note: In instance 't'
+   12 |     @e;  
+      |     ^
+                                : ... Suggest make caller 'function calls_timing_ctl' a task
+   11 |   function void calls_timing_ctl;
+      |                 ^~~~~~~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_func_bad_time.v:17:5: Functions cannot contain time-controlling statements (IEEE 1800-2023 13.4)
+                                : ... note: In instance 't'
+   17 |     wait (s);  
+      |     ^~~~
+                                : ... Suggest make caller 'function calls_timing_ctl' a task
+   11 |   function void calls_timing_ctl;
+      |                 ^~~~~~~~~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_func_bad_time.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(verilator_flags2=['--timing'], fails=test.vlt_all, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_func_bad_time.v

@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  event e;
+  logic s;
+
+  function void calls_timing_ctl;
+    @e; // <--- Bad IEEE 1800-2023 13.4 time-controlling
+    fork // <--- Bad IEEE 1800-2023 13.4 time-controlling
+    join
+    fork // <--- Bad IEEE 1800-2023 13.4 time-controlling
+    join_any
+    wait (s); // <--- Bad IEEE 1800-2023 13.4 time-controlling
+    // TODO wait_order (e);
+    // TODO ##
+    // TODO expect
+  endfunction
+endmodule