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Support ++,--,+= etc as standalone statements.

This commit is contained in:
Wilson Snyder 2010-12-07 20:18:47 -05:00
parent e6443f1981
commit d6ac5e5001
4 changed files with 56 additions and 12 deletions
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2
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@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
*** Add -F option to read relative option files, bug297. [Neil Hamilton] *** Add -F option to read relative option files, bug297. [Neil Hamilton]
*** Support ++,--,+= etc as standalone statements. [Alex Solomatnikov]
*** Suppress WIDTH warnings when adding/subtracting 1'b1. *** Suppress WIDTH warnings when adding/subtracting 1'b1.
**** When running with VERILATOR_ROOT, optionally find binaries under bin. **** When running with VERILATOR_ROOT, optionally find binaries under bin.

6
bin/verilator
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@ -2053,6 +2053,12 @@ supply1, task, time, tri, typedef, var, vectored, while, wire, xnor, xor
Generally supported. Generally supported.
=item ++, -- operators
Increment/decrement can only be used as standalone statements or in for
loops. They cannot be used as side effect operators inside more complicate
expressions ("a = b++;").
=item chandle =item chandle
Treated as a "longint"; does not yet warn about operations that are Treated as a "longint"; does not yet warn about operations that are

45
src/verilog.y
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@ -1830,7 +1830,7 @@ statement_item<nodep>: // IEEE: statement_item
| unique_priorityE yIF '(' expr ')' stmtBlock yELSE stmtBlock | unique_priorityE yIF '(' expr ')' stmtBlock yELSE stmtBlock
{ $$ = new AstIf($2,$4,$6,$8); } { $$ = new AstIf($2,$4,$6,$8); }
// //
//UNSUP finc_or_dec_expression ';' { } | finc_or_dec_expression ';' { $$ = $1; }
// // IEEE: inc_or_dec_expression // // IEEE: inc_or_dec_expression
// // Below under expr // // Below under expr
// //
@ -1920,17 +1920,38 @@ foperator_assignment<nodep>: // IEEE: operator_assignment (for first part of exp
| '{' variable_lvalueConcList '}' '=' delayE expr { $$ = new AstAssign($4,$2,$6); } | '{' variable_lvalueConcList '}' '=' delayE expr { $$ = new AstAssign($4,$2,$6); }
// //
//UNSUP ~f~exprLvalue '=' delay_or_event_controlE expr { UNSUP } //UNSUP ~f~exprLvalue '=' delay_or_event_controlE expr { UNSUP }
//UNSUP ~f~exprLvalue yP_PLUSEQ expr { UNSUP } //UNSUP ~f~exprLvalue yP_PLUS(etc) expr { UNSUP }
//UNSUP ~f~exprLvalue yP_MINUSEQ expr { UNSUP } | idClassSel yP_PLUSEQ expr { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_TIMESEQ expr { UNSUP } | idClassSel yP_MINUSEQ expr { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_DIVEQ expr { UNSUP } | idClassSel yP_TIMESEQ expr { $$ = new AstAssign($2,$1,new AstMul ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_MODEQ expr { UNSUP } | idClassSel yP_DIVEQ expr { $$ = new AstAssign($2,$1,new AstDiv ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_ANDEQ expr { UNSUP } | idClassSel yP_MODEQ expr { $$ = new AstAssign($2,$1,new AstModDiv ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_OREQ expr { UNSUP } | idClassSel yP_ANDEQ expr { $$ = new AstAssign($2,$1,new AstAnd ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_XOREQ expr { UNSUP } | idClassSel yP_OREQ expr { $$ = new AstAssign($2,$1,new AstOr ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_SLEFTEQ expr { UNSUP } | idClassSel yP_XOREQ expr { $$ = new AstAssign($2,$1,new AstXor ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_SRIGHTEQ expr { UNSUP } | idClassSel yP_SLEFTEQ expr { $$ = new AstAssign($2,$1,new AstShiftL ($2,$1->cloneTree(true),$3)); }
//UNSUP ~f~exprLvalue yP_SSRIGHTEQ expr { UNSUP } | idClassSel yP_SRIGHTEQ expr { $$ = new AstAssign($2,$1,new AstShiftR ($2,$1->cloneTree(true),$3)); }
| idClassSel yP_SSRIGHTEQ expr { $$ = new AstAssign($2,$1,new AstShiftRS($2,$1->cloneTree(true),$3)); }
//
| '{' variable_lvalueConcList '}' yP_PLUSEQ expr { $$ = new AstAssign($4,$2,new AstAdd ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_MINUSEQ expr { $$ = new AstAssign($4,$2,new AstSub ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_TIMESEQ expr { $$ = new AstAssign($4,$2,new AstMul ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_DIVEQ expr { $$ = new AstAssign($4,$2,new AstDiv ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_MODEQ expr { $$ = new AstAssign($4,$2,new AstModDiv ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_ANDEQ expr { $$ = new AstAssign($4,$2,new AstAnd ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_OREQ expr { $$ = new AstAssign($4,$2,new AstOr ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_XOREQ expr { $$ = new AstAssign($4,$2,new AstXor ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_SLEFTEQ expr { $$ = new AstAssign($4,$2,new AstShiftL ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_SRIGHTEQ expr { $$ = new AstAssign($4,$2,new AstShiftR ($4,$2->cloneTree(true),$5)); }
| '{' variable_lvalueConcList '}' yP_SSRIGHTEQ expr { $$ = new AstAssign($4,$2,new AstShiftRS($4,$2->cloneTree(true),$5)); }
;
finc_or_dec_expression<nodep>: // ==IEEE: inc_or_dec_expression
//UNSUP: Generic scopes in incrementes
varRefBase yP_PLUSPLUS { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); }
| varRefBase yP_MINUSMINUS { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),new AstConst($2,V3Number($2,"'b1")))); }
| yP_PLUSPLUS varRefBase { $$ = new AstAssign($1,$2,new AstAdd ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); }
| yP_MINUSMINUS varRefBase { $$ = new AstAssign($1,$2,new AstSub ($1,$2->cloneTree(true),new AstConst($1,V3Number($1,"'b1")))); }
; ;
//************************************************ //************************************************

15
test_regress/t/t_math_const.v
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@ -90,6 +90,21 @@ module t (/*AUTOARG*/
// Wide decimal // Wide decimal
if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop; if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop;
if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop; if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop;
// Increments
w32 = 12; w32++; if (w32 != 13) $stop;
w32 = 12; ++w32; if (w32 != 13) $stop;
w32 = 12; w32--; if (w32 != 11) $stop;
w32 = 12; --w32; if (w32 != 11) $stop;
w32 = 12; w32 += 2; if (w32 != 14) $stop;
w32 = 12; w32 -= 2; if (w32 != 10) $stop;
w32 = 12; w32 *= 2; if (w32 != 24) $stop;
w32 = 12; w32 /= 2; if (w32 != 6) $stop;
w32 = 12; w32 &= 6; if (w32 != 4) $stop;
w32 = 12; w32 |= 15; if (w32 != 15) $stop;
w32 = 12; w32 ^= 15; if (w32 != 3) $stop;
w32 = 12; w32 >>= 1; if (w32 != 6) $stop;
w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
end end
if (cyc==2) begin if (cyc==2) begin
win <= 32'h123123; win <= 32'h123123;