Cover sequence-referenced-outside-assertion message via nested sequence test

test_regress/t/t_assert_seq_event_unsup.v

@@ -10,8 +10,8 @@ module t (
   bit a, b;
   logic g = 0;
 
-  // A module default clocking does NOT make a clockless sequence legal as an
-  // event (confirmed against Questa); s_unclocked below stays E_UNSUPPORTED.
+  // Clockless `@seq` stays E_UNSUPPORTED even under a default clocking, matching
+  // Questa; whether 9.4.2.4 should inherit it here is an open PR question.
   default clocking @(posedge clk);
   endclocking
 

test_regress/t/t_sequence_ref_unsup.out

@@ -1,5 +1,6 @@
-%Error-UNSUPPORTED: t/t_sequence_ref_unsup.v:14:6: Unsupported: '@' event control on a sequence without a clocking event
-   14 |     @s_one;
-      |      ^~~~~
+%Error-UNSUPPORTED: t/t_sequence_ref_unsup.v:9:12: Unsupported: sequence referenced outside assertion property
+                                                 : ... note: In instance 't'
+    9 |   sequence s_one;
+      |            ^~~~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_sequence_ref_unsup.v

@@ -10,10 +10,10 @@ module t;
     1;
   endsequence
 
-  initial begin
-    @s_one;
-    $display("got sequence");
-    $finish;
-  end
+  // s_one is referenced only from another sequence that is never expanded into
+  // an assertion, so it is left referenced outside any assertion property.
+  sequence s_two;
+    s_one ##1 1;
+  endsequence
 
 endmodule