Tests (#3806) (#3807)

test_regress/t/t_case_duplicated_if.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_case_duplicated_if.v

@@ -0,0 +1,57 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// bug3806
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   reg [65:0] idx /*verilator public*/; initial idx = 1;
+
+   wire unlikely = idx > 200;
+
+   typedef enum logic {UP, DOWN} dir_t;
+
+   dir_t direction;
+
+   always_comb direction = idx % 2 == 0 ? UP : DOWN;
+
+   int ups;  // Make computable
+
+   always @(posedge clk) begin
+      if (idx > 100) begin
+`ifdef TEST_VERBOSE
+         $write("ups = %0d\n", ups);
+`endif
+         if (ups != 50049) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+
+      if (direction == UP)
+        ++ups;
+      else if (direction == UP)
+        ++ups;
+      else
+        ups += 1000;
+
+      case (direction)
+        DOWN: idx = idx+3;
+        UP: idx = idx-1;
+        default: begin
+           // This if just gets rid of branch pred on default^
+           if (unlikely == '1) begin
+              $write("never\n");
+           end
+        end
+      endcase
+   end
+
+endmodule

test_regress/t/t_if_same_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 0,  # bug3806 - this test should fail but does not
+    # expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_if_same_bad.v

@@ -0,0 +1,58 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// bug3806
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+
+   reg [3:0]  in;
+   tri [3:0]  bus = in;
+
+   int        never_driven;
+   int        never_forced;
+
+   task force_bus;
+      force bus[1:0] = 2'b10;
+   endtask
+
+   task release_bus;
+      release bus;
+   endtask
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 0) begin
+         in <= 4'b0101;
+      end
+      else if (cyc == 10) begin
+         $display("10");
+      end
+      else if (cyc == 11) begin
+         $display("11");
+      end
+      //
+      // bus
+      else if (cyc == 10) begin  // Should warn
+         $display("10b");
+      end
+      else if (cyc == 11) begin  // Should warn
+         $display("11b");
+      end
+      //
+      else if (cyc == 99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule