Support 'for' initialization with comma
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@ -3897,8 +3897,7 @@ for_initialization<nodep>: // ==IEEE: for_initialization + for_variable_dec
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for_initializationItemList<nodep>: // IEEE: [for_variable_declaration...]
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for_initializationItemList<nodep>: // IEEE: [for_variable_declaration...]
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for_initializationItem { $$ = $1; }
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for_initializationItem { $$ = $1; }
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| for_initializationItemList ',' for_initializationItem
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| for_initializationItemList ',' for_initializationItem { $$ = addNextNull($1, $3); }
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{ $$ = $1; BBUNSUP($2, "Unsupported: for loop initialization after the first comma"); }
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;
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;
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for_initializationItem<nodep>: // IEEE: variable_assignment + for_variable_declaration
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for_initializationItem<nodep>: // IEEE: variable_assignment + for_variable_declaration
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@ -8,11 +8,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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# Version 2.0.
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(linter => 1);
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scenarios(simulator => 1);
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lint(
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compile(
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fails => 1,
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);
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expect_filename => $Self->{golden_filename},
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execute(
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check_finished => 1,
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);
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);
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ok(1);
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ok(1);
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@ -0,0 +1,61 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkc(expc) \
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do begin \
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if (c !== expc) begin \
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$write("%%Error: %s:%0d: a=%0d b=%0d c=%0d expc=%0d\n", `__FILE__,`__LINE__, a, b, c, (expc)); \
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$stop; \
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end \
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a=0; b=0; c=0; \
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end while(0);
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module t (/*AUTOARG*/);
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int a, b, c;
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initial begin
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for (; ; ) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; ; a = a + 1) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; ; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; a < 3; ) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; a < 3; a = a + 1) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end
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`checkc(1);
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for (a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
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`checkc(2);
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for (a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
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`checkc(5);
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for (a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
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`checkc(6);
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for (int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
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`checkc(2);
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for (int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
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`checkc(5);
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for (int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
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`checkc(6);
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for (var int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
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`checkc(2);
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for (var int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
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`checkc(5);
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for (var int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
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`checkc(6);
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for (int a = 1, int b = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end
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`checkc(3);
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for (int a = 1, int b = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end
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`checkc(7);
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for (int a = 1, int b = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end
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`checkc(8);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -1,11 +0,0 @@
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%Error-UNSUPPORTED: t/t_for_comma_bad.v:27:23: Unsupported: for loop initialization after the first comma
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27 | for (integer a=0, integer b=0; a<1; ) ;
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| ^
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_for_comma_bad.v:28:23: Unsupported: for loop initialization after the first comma
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28 | for (integer a=0, integer b=0; a<1; a=a+1) ;
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| ^
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%Error-UNSUPPORTED: t/t_for_comma_bad.v:29:23: Unsupported: for loop initialization after the first comma
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29 | for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ;
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| ^
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%Error: Exiting due to
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@ -1,34 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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integer a, b;
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initial begin
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for (; ; ) ;
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for (; ; a=a+1) ;
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for (; ; a=a+1, b=b+1) ;
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for (; a<1; ) ;
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for (; a<1; a=a+1) ;
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for (; a<1; a=a+1, b=b+1) ;
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for (a=0; a<1; ) ;
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for (a=0; a<1; a=a+1) ;
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for (a=0; a<1; a=a+1, b=b+1) ;
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for (integer a=0; a<1; ) ;
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for (integer a=0; a<1; a=a+1) ;
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for (integer a=0; a<1; a=a+1, b=b+1) ;
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for (var integer a=0; a<1; ) ;
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for (var integer a=0; a<1; a=a+1) ;
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for (var integer a=0; a<1; a=a+1, b=b+1) ;
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for (integer a=0, integer b=0; a<1; ) ;
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for (integer a=0, integer b=0; a<1; a=a+1) ;
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for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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