Tests: Redo uvm test and package to be version based and use uvm_info

nodist/uvm_pkg_packer

@@ -0,0 +1,92 @@
+#!/usr/bin/env python3
+# mypy: disallow-untyped-defs
+# pylint: disable=
+######################################################################
+
+import argparse
+import re
+import sys
+
+######################################################################
+
+
+def process() -> None:
+    in_header = True
+    for line in sys.stdin:
+        line = line.rstrip()
+        line = line.expandtabs(tabsize=8)
+        line = re.sub(r', +', ', ', line)
+        line = re.sub(r'"/[^"]+/src/', '"t/uvm/src/', line)
+
+        # Replace header
+        if in_header:
+            if re.match(r'^//', line):
+                continue
+            else:
+                in_header = False
+                print_header()
+        in_header = False
+
+        # Drop some unneeded items
+        if re.match(r'^`begin_keywords ', line):
+            continue
+        if re.match(r'^`line ', line):
+            continue
+        if re.match(r'^\s*$', line):
+            continue
+
+        if re.match(r'^ *endpackage', line):
+            print(line)
+            break
+
+        print(line)
+
+
+def print_header() -> None:
+    print("// DESCR"
+          "IPTION: Verilator: Concatenated UVM header for internal testing")
+    print("// SPDX-"
+          "License-Identifier: Apache-2.0")
+    print("//----------------------------------------------------------------------")
+    print("// To recreate:")
+    print("//   Using verilator_ext_tests:")
+    print("//     " + Args.test_name + " --gold")
+    # Copy the copyright header from original sources
+    with open(Args.uvm_header_filename, 'r', encoding="utf8") as fh:
+        for line in fh:
+            line = line.strip()
+            line = line.expandtabs(tabsize=8)
+            if not re.match(r'^//', line):
+                break
+            print(line)
+
+
+#######################################################################
+#######################################################################
+
+parser = argparse.ArgumentParser(
+    allow_abbrev=False,
+    formatter_class=argparse.RawDescriptionHelpFormatter,
+    description="""uvm_pkg_packer is used to create the test_regress
+uvm_pkg libraries from sources in verilator_ext_test repository's tests.""",
+    epilog="""Copyright 2025-2025 by Wilson Snyder. This program is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License Version 3 or the Perl Artistic License
+Version 2.0.
+
+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""")
+
+parser.add_argument('--debug', action='store_true', help='enable debug')
+parser.add_argument('--test-name', type=str, required=True, help='name of test to run to recreate')
+parser.add_argument('--uvm-header-filename',
+                    type=str,
+                    required=True,
+                    help='filename of uvm_pkg.sv')
+
+Args = parser.parse_args()
+process()
+
+######################################################################
+# Local Variables:
+# compile-command: "cd $VE && t/t_uvm_hello_v2017_1_0_nodpi.py"
+# End:

test_regress/t/t_dist_copyright.py

@@ -47,9 +47,7 @@ EXEMPT_FILES_LIST = """
     test_regress/t/t_sequence_first_match_unsup.v
     test_regress/t/tsub/t_flag_f_tsub.v
     test_regress/t/tsub/t_flag_f_tsub_inc.v
-    test_regress/t/uvm/dpi
-    test_regress/t/uvm/uvm_pkg_all.svh
-    test_regress/t/uvm/uvm_pkg_todo.svh
+    test_regress/t/uvm/
     verilator.pc.in
     """
 

test_regress/t/t_uvm_all.py

@@ -1,23 +0,0 @@
-#!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2024 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-import vltest_bootstrap
-
-test.scenarios('vlt')
-
-test.compile(
-    v_flags2=[
-        "--binary -j 0 +incdir+t/uvm",  #
-        "--error-limit 200 --debug-exit-uvm"
-    ],
-    verilator_make_gmake=False)
-
-#test.execute()
-
-test.passes()

test_regress/t/t_uvm_all.v

@@ -1,18 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2023 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-`define UVM_NO_DPI
-
-`include "uvm_pkg_all.svh"
-
-module t;
-
-   initial begin
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
-
-endmodule

test_regress/t/t_uvm_hello.v

@@ -0,0 +1,18 @@
+// -*- Verilog -*-
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// Test requires command line be passed uvm_pkg.sv before this filename
+
+// verilator lint_off DECLFILENAME
+
+module t;
+  import uvm_pkg::*;
+  initial begin
+    // verilator lint_off WIDTHTRUNC
+    `uvm_info("TOP", "Hello World!", UVM_MEDIUM);
+  end
+endmodule

test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py

@@ -10,12 +10,17 @@
 import vltest_bootstrap
 
 test.scenarios('vlt')
+test.top_filename = 't/t_uvm_hello.v'
 
 if test.have_dev_gcov:
     test.skip("Test suite intended for full dev coverage without needing this test")
 
-test.compile(v_flags2=["--timing", "+incdir+t/uvm", "t/t_uvm_todo.vlt", "-j 0"],
-             make_flags=['-k'],
-             verilator_make_gmake=False)
+test.compile(v_flags2=[
+    "--binary",
+    "-j 0",
+    "-Wall",
+    "+incdir+t/uvm",  #
+    "t/uvm/uvm_pkg_all_v2017_1_0_nodpi.svh",
+])
 
 test.passes()

test_regress/t/t_uvm_todo.v

@@ -1,18 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2023 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-`define UVM_NO_DPI
-
-`include "uvm_pkg_todo.svh"
-
-module t;
-
-  initial begin
-    $write("*-* All Finished *-*\n");
-    $finish;
-  end
-
-endmodule

test_regress/t/t_uvm_todo.vlt

@@ -1,7 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2024 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-`verilator_config