luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 10:03:44 +02:00
Code Issues Packages Projects Releases Wiki Activity

Internals: Cleanup some misnamed classes. No functional change.

Browse Source
This commit is contained in:
Wilson Snyder
2019-10-05 08:17:21 -04:00
parent f1c04b5d25
commit d472ef63e9
49 changed files with 260 additions and 253 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/V3Order.cpp
+8 -8
View File
@@ -279,7 +279,7 @@ private:
if (AstVarRef* varrefp = VN_CAST(nodep->rhsp(), VarRef)) {
this->visit(varrefp);
m_rightClkWidth = varrefp->width();
if (varrefp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
if (varrefp->varp()->attrClocker() == VVarAttrClocker::CLOCKER_YES) {
if (m_inClocked) {
varrefp->v3warn(CLKDATA, "Clock used as data (on rhs of assignment) in sequential block "
<<varrefp->prettyNameQ()<<endl);
@@ -307,8 +307,8 @@ private:
}
const AstVarRef* lhsp = VN_CAST(nodep->lhsp(), VarRef);
if (lhsp && (lhsp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_UNKNOWN)) {
lhsp->varp()->attrClocker(AstVarAttrClocker::CLOCKER_YES); // mark as clocker
if (lhsp && (lhsp->varp()->attrClocker() == VVarAttrClocker::CLOCKER_UNKNOWN)) {
lhsp->varp()->attrClocker(VVarAttrClocker::CLOCKER_YES); // mark as clocker
m_newClkMarked = true; // enable a further run since new clocker is marked
UINFO(5, "node is newly marked as clocker by assignment "<<lhsp<<endl);
}
@@ -316,7 +316,7 @@ private:
}
virtual void visit(AstVarRef* nodep) {
if (m_inAss && nodep->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
if (m_inAss && nodep->varp()->attrClocker() == VVarAttrClocker::CLOCKER_YES) {
if (m_inClocked) {
nodep->v3warn(CLKDATA,
"Clock used as data (on rhs of assignment) in sequential block "
@@ -395,7 +395,7 @@ private:
VL_DEBUG_FUNC; // Declare debug()
virtual void visit(AstNodeAssign* nodep) {
if (const AstVarRef* varrefp = VN_CAST(nodep->lhsp(), VarRef)) {
if (varrefp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
if (varrefp->varp()->attrClocker() == VVarAttrClocker::CLOCKER_YES) {
m_clkAss = true;
UINFO(6, "node was marked as clocker "<<varrefp<<endl);
}
@@ -722,7 +722,7 @@ protected:
private:
// STATS
V3Double0 m_statCut[OrderVEdgeType::_ENUM_END]; // Count of each edge type cut
VDouble0 m_statCut[OrderVEdgeType::_ENUM_END]; // Count of each edge type cut
// TYPES
enum VarUsage { VU_NONE=0, VU_CON=1, VU_GEN=2 };
@@ -1075,7 +1075,7 @@ private:
con = false;
}
if (m_inClkAss && (varscp->varp()->attrClocker()
!= AstVarAttrClocker::CLOCKER_YES)) {
!= VVarAttrClocker::CLOCKER_YES)) {
con = false;
UINFO(4, "nodep used as clock_enable "<<varscp
<<" in "<<m_logicVxp->nodep()<<endl);
@@ -1105,7 +1105,7 @@ private:
// If the lhs is a clocker, avoid marking that as circular by
// putting a hard edge instead of normal cuttable
if (varscp->varp()->attrClocker()
== AstVarAttrClocker::CLOCKER_YES) {
== VVarAttrClocker::CLOCKER_YES) {
new OrderEdge(&m_graph, m_logicVxp, varVxp, WEIGHT_NORMAL);
} else {
new OrderComboCutEdge(&m_graph, m_logicVxp, varVxp);