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Internals: Cleanup some misnamed classes. No functional change.
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+9
-9
@@ -326,10 +326,10 @@ private:
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bool m_activeReducible; // Is activation block reducible?
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bool m_inSenItem; // Underneath AstSenItem; any varrefs are clocks
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bool m_inSlow; // Inside a slow structure
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V3Double0 m_statSigs; // Statistic tracking
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V3Double0 m_statRefs; // Statistic tracking
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V3Double0 m_statDedupLogic; // Statistic tracking
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V3Double0 m_statAssignMerged; // Statistic tracking
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VDouble0 m_statSigs; // Statistic tracking
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VDouble0 m_statRefs; // Statistic tracking
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VDouble0 m_statDedupLogic; // Statistic tracking
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VDouble0 m_statAssignMerged; // Statistic tracking
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// METHODS
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void iterateNewStmt(AstNode* nodep, const char* nonReducibleReason, const char* consumeReason) {
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@@ -1147,7 +1147,7 @@ private:
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// NODE STATE
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// AstVarScope::user2p -> bool: already visited
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// AstUser2InUse m_inuser2; (Allocated for use in GateVisitor)
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V3Double0 m_numDeduped; // Statistic tracking
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VDouble0 m_numDeduped; // Statistic tracking
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GateDedupeVarVisitor m_varVisitor; // Looks for a dupe of the logic
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int m_depth; // Iteration depth
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@@ -1228,7 +1228,7 @@ public:
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void dedupeTree(GateVarVertex* vvertexp) {
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vvertexp->accept(*this);
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}
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V3Double0 numDeduped() { return m_numDeduped; }
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VDouble0 numDeduped() { return m_numDeduped; }
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};
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//----------------------------------------------------------------------
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@@ -1268,7 +1268,7 @@ private:
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AstActive* m_activep;
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GateLogicVertex* m_logicvp;
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V3Graph* m_graphp;
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V3Double0 m_numMergedAssigns; // Statistic tracking
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VDouble0 m_numMergedAssigns; // Statistic tracking
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// assemble two Sel into one if possible
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@@ -1377,7 +1377,7 @@ public:
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void mergeAssignsTree(GateVarVertex* vvertexp) {
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vvertexp->accept(*this);
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}
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V3Double0 numMergedAssigns() { return m_numMergedAssigns; }
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VDouble0 numMergedAssigns() { return m_numMergedAssigns; }
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};
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@@ -1580,7 +1580,7 @@ void GateVisitor::decomposeClkVectors() {
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for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
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if (GateVarVertex* vertp = dynamic_cast<GateVarVertex*>(itp)) {
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AstVarScope* vsp = vertp->varScp();
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if (vsp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
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if (vsp->varp()->attrClocker() == VVarAttrClocker::CLOCKER_YES) {
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if (vsp->varp()->width() > 1) {
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UINFO(9,"Clocker > 1 bit, not decomposing: "<<vsp<<endl);
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} else {
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