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Fix for variable typing, bug205.

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This commit is contained in:
Wilson Snyder
2010-01-19 19:27:36 -05:00
parent 5d57263a15
commit d2bce042a5
2 changed files with 6 additions and 4 deletions
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src/verilog.y
+4 -4
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@@ -1945,10 +1945,10 @@ caseCondList<nodep>: // IEEE: part of case_item
// "datatype id = x {, id = x }" | "yaId = x {, id=x}" is legal
for_initialization<nodep>: // ==IEEE: for_initialization + for_variable_declaration + extra terminating ";"
// // IEEE: for_variable_declaration
data_type idAny/*new*/ '=' expr ';'
{ VARDTYPE($1);
$$ = VARDONEA(*$2,NULL,NULL);
$$->addNext(new AstAssign($3,new AstVarRef($3,*$2,true),$4));}
varRESET data_type idAny/*new*/ '=' expr ';'
{ VARDTYPE($2);
$$ = VARDONEA(*$3,NULL,NULL);
$$->addNext(new AstAssign($4,new AstVarRef($4,*$3,true),$5));}
| varRefBase '=' expr ';' { $$ = new AstAssign($2,$1,$3); }
//UNSUP: List of initializations
;