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Commentary (#7532) (#7533)

This commit is contained in:
Wilson Snyder 2026-05-04 18:01:55 -04:00
parent 9a24b3d7ba
commit d2ae094d43
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docs/guide/connecting.rst
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@ -184,7 +184,7 @@ Verilog, put in our.v:
initial begin initial begin
$display("%x + %x = %x", 1, 2, add(1,2)); $display("%x + %x = %x", 1, 2, add(1,2));
endtask end
Then after Verilating, Verilator will create a file Vour__Dpi.h with the Then after Verilating, Verilator will create a file Vour__Dpi.h with the
prototype to call this function: prototype to call this function: