Commentary (#7532) (#7533)

2026-05-04 18:01:55 -04:00 · 2026-05-04 18:01:55 -04:00 · d2ae094d43
parent 9a24b3d7ba
commit d2ae094d43
1 changed files with 1 additions and 1 deletions
--- a/docs/guide/connecting.rst
+++ b/docs/guide/connecting.rst
@ -184,7 +184,7 @@ Verilog, put in our.v:

   initial begin
     $display("%x + %x = %x", 1, 2, add(1,2));
-   endtask
+   end

 Then after Verilating, Verilator will create a file Vour__Dpi.h with the
 prototype to call this function: