Add error on `solve before` of `randc` variable.

Changes

@@ -20,6 +20,7 @@ Verilator 5.031 devel
 * Add error on `wait` with missing `.triggered` (#4457).
 * Add error when improperly storing to parameter (#5147). [Gökçe Aydos]
 * Add coverage point hierarchy to coverage reports (#5575) (#5576). [Andrew Nolte]
+* Add error on `solve before` of `randc` variable.
 * Fix can't locate scope error in interface task delayed assignment (#5462) (#5568). [Zhou Shen]
 * Fix BLKANDNBLK for for VARXREFs (#5569). [Todd Strader]
 * Fix VPI error instead of fatal for vpi_get_value() on large signals (#5571). [Todd Strader]

src/V3Randomize.cpp

@@ -401,6 +401,15 @@ class RandomizeMarkVisitor final : public VNVisitor {
             }
         }
     }
+    void visit(AstConstraintBefore* nodep) override {
+        nodep->foreach([&](AstVarRef* const refp) {
+            if (refp->varp() && refp->varp()->isRandC()) {
+                nodep->v3error(
+                    "Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9)");
+            }
+        });
+        iterateChildrenConst(nodep);
+    }
     void visit(AstConstraintExpr* nodep) override {
         VL_RESTORER(m_constraintExprp);
         m_constraintExprp = nodep;

test_regress/t/t_randomize_before_randc_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_randomize_before_randc_bad.v:11:29: Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9)
+                                              : ... note: In instance 't'
+   11 |     constraint raint2_bad { solve b1 before b2; }   
+      |                             ^~~~~
+%Error: Exiting due to

test_regress/t/t_randomize_before_randc_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_randomize_before_randc_bad.v

@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls1;
+    rand bit b1;
+    randc int b2;
+
+    constraint raint2_bad { solve b1 before b2; }  // BAD no randc vars here
+endclass
+
+module t (/*AUTOARG*/);
+endmodule