Tests: Add test for (#4040).

Changes

@@ -316,7 +316,7 @@ Verilator 5.028 2024-08-21
 * Add parsing but otherwise ignore std::randomize (#5354). [Arkadiusz Kozdra, Antmicro Ltd.]
 * Add Verilated cc define when `--timing` used (#5383). [Kaleb Barrett]
 * Improve emitted code to use a reference for VlSelf (#5254). [Yangyu Chen]
-* Fix monitor block sensitivity items (#4400) (#5294). [Udaya Raj Subedi]
+* Fix monitor block sensitivity items (#4040) (#4400) (#5294). [Udaya Raj Subedi]
 * Fix fusing macro arguments to not ignore whitespace (#5061). [Tudor Timi]
 * Fix optimized-out sensitivity trees with `--timing` (#5080) (#5349). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix classes/modules of case-similar names (#5109). [Arkadiusz Kozdra]

test_regress/t/t_sys_monitor_changes.out

@@ -0,0 +1,6 @@
+[0] a=0 b=0
+[101] a=10 b=0
+[111] a=10 b=20
+[121] a=11 b=20
+[131] a=11 b=22
+*-* All Finished *-*

test_regress/t/t_sys_monitor_changes.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute(expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_sys_monitor_changes.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   bit clk;
+   int a, b;
+
+   always #10 clk = ~clk;
+
+   initial begin
+      $monitor("[%0t] a=%0d b=%0d", $time, a, b);
+      #1;  // So not on clock edge
+      #100;
+      a = 10;
+      #10;
+      b = 20;
+      #10;
+      a = 11;
+      #10;
+      b = 22;
+      #100;
+      #10;
+      $monitoroff;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule