Fix dpi export pointers (#7742) (#7751)

Fixes #7742.
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Yilin Li 2026-06-10 15:38:41 +02:00 committed by GitHub
parent de0236be2f
commit d1319cf81e
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4 changed files with 62 additions and 2 deletions

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@ -325,3 +325,4 @@ Yogish Sekhar
24bit-xjkp
Zubin Jain
Muzaffer Kal
Yilin Li

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@ -573,8 +573,14 @@ public:
+ "\", " + std::to_string(nodep->fileline()->lineno()) + ")->"),
memberVarp, resetp->constructing());
} else {
AstVar* const varp = VN_AS(fromp, NodeVarRef)->varp();
emitVarReset("", varp, resetp->constructing());
AstNodeVarRef* const fromVarRefp = VN_AS(fromp, NodeVarRef);
AstVar* const varp = fromVarRefp->varp();
const string prefix
= fromVarRefp->selfPointer().isEmpty()
? ""
: dereferenceString(
VN_AS(fromp, NodeVarRef)->selfPointerProtect(m_useSelfForThis));
emitVarReset(prefix, varp, resetp->constructing());
}
return;
}

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@ -0,0 +1,20 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
# 9-Jun-2026: Modifications for this test contributed by Yilin Li.
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=["--binary"])
test.execute()
test.passes()

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@ -0,0 +1,33 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of either the GNU Lesser General Public License Version 3
// or the Perl Artistic License Version 2.0.
// SPDX-FileCopyrightText: 2020 Wilson Snyder
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
// 9-Jun-2026: Modifications for this test contributed by Yilin Li.
export "DPI-C" task readHEX;
export "DPI-C" task loadHEX;
task readHEX;
input string file;
output logic [7:0] stimuli[32'h00010000];
$readmemh(file, stimuli);
endtask
task loadHEX;
input string file;
logic [7:0] stimuli[32'h00010000];
readHEX(file, stimuli);
endtask
module tb ();
logic [7:0] result[32'h00010000];
initial begin
loadHEX("dummy");
end
endmodule