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Support signal types in FST dumps, bug1358.

This commit is contained in:
Wilson Snyder 2018-10-04 20:24:41 -04:00
parent 8ef9ac7dba
commit d11592cadd
12 changed files with 865 additions and 760 deletions
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11
include/verilated_fst_c.cpp
View File

@ -94,8 +94,9 @@ void VerilatedFst::module(const std::string& name) {
//=============================================================================
// Decl
void VerilatedFst::declSymbol(vluint32_t code, const char* name, VerilatedVarFlags varflags,
int arraynum, vluint32_t len, fstVarType vartype) {
void VerilatedFst::declSymbol(vluint32_t code, const char* name, fstVarDir vardir,
fstVarType vartype,
int arraynum, vluint32_t len) {
std::pair<Code2SymbolType::iterator, bool> p
= m_code2symbol.insert(std::make_pair(code, (fstHandle)(0)));
std::istringstream nameiss(name);
@ -134,12 +135,6 @@ void VerilatedFst::declSymbol(vluint32_t code, const char* name, VerilatedVarFla
name_ss << "(" << arraynum << ")";
std::string name_str = name_ss.str();
static fstVarDir vardir;
if ((varflags & VLVD_INOUT) == VLVD_INOUT) vardir = FST_VD_INOUT;
else if ((varflags & VLVD_IN) == VLVD_IN) vardir = FST_VD_INPUT;
else if ((varflags & VLVD_OUT) == VLVD_OUT) vardir = FST_VD_OUTPUT;
else vardir = FST_VD_IMPLICIT;
if (p.second) { // New
p.first->second = fstWriterCreateVar(m_fst, vartype, vardir, len, name_str.c_str(), 0);
assert(p.first->second);

29
include/verilated_fst_c.h
View File

@ -55,8 +55,9 @@ private:
std::list<std::string> m_curScope;
// CONSTRUCTORS
VL_UNCOPYABLE(VerilatedFst);
void declSymbol(vluint32_t code, const char* name, VerilatedVarFlags varflags,
int arraynum, vluint32_t len, fstVarType vartype);
void declSymbol(vluint32_t code, const char* name,
fstVarDir vardir, fstVarType vartype,
int arraynum, vluint32_t len);
// helpers
std::vector<char> m_valueStrBuffer;
char* word2Str(vluint32_t newval, int bits);
@ -96,29 +97,29 @@ public:
/// Inside dumping routines, declare a module
void module(const std::string& name);
/// Inside dumping routines, declare a signal
void declBit(vluint32_t code, const char* name, VerilatedVarFlags varflags,
void declBit(vluint32_t code, const char* name, fstVarDir vardir, fstVarType vartype,
int arraynum) {
declSymbol(code, name, varflags, arraynum, 1, FST_VT_VCD_WIRE);
declSymbol(code, name, vardir, vartype, arraynum, 1);
}
void declBus(vluint32_t code, const char* name, VerilatedVarFlags varflags,
void declBus(vluint32_t code, const char* name, fstVarDir vardir, fstVarType vartype,
int arraynum, int msb, int lsb) {
declSymbol(code, name, varflags, arraynum, msb - lsb + 1, FST_VT_VCD_WIRE);
declSymbol(code, name, vardir, vartype, arraynum, msb - lsb + 1);
}
void declDouble(vluint32_t code, const char* name, VerilatedVarFlags varflags,
void declDouble(vluint32_t code, const char* name, fstVarDir vardir, fstVarType vartype,
int arraynum) {
declSymbol(code, name, varflags, arraynum, 2, FST_VT_VCD_REAL);
declSymbol(code, name, vardir, vartype, arraynum, 2);
}
void declFloat(vluint32_t code, const char* name, VerilatedVarFlags varflags,
void declFloat(vluint32_t code, const char* name, fstVarDir vardir, fstVarType vartype,
int arraynum) {
declSymbol(code, name, varflags, arraynum, 1, FST_VT_SV_SHORTREAL);
declSymbol(code, name, vardir, vartype, arraynum, 1);
}
void declQuad(vluint32_t code, const char* name, VerilatedVarFlags varflags,
void declQuad(vluint32_t code, const char* name, fstVarDir vardir, fstVarType vartype,
int arraynum, int msb, int lsb) {
declSymbol(code, name, varflags, arraynum, msb - lsb + 1, FST_VT_VCD_WIRE);
declSymbol(code, name, vardir, vartype, arraynum, msb - lsb + 1);
}
void declArray(vluint32_t code, const char* name, VerilatedVarFlags varflags,
void declArray(vluint32_t code, const char* name, fstVarDir vardir, fstVarType vartype,
int arraynum, int msb, int lsb) {
declSymbol(code, name, varflags, arraynum, msb - lsb + 1, FST_VT_VCD_WIRE);
declSymbol(code, name, vardir, vartype, arraynum, msb - lsb + 1);
}
/// Inside dumping routines, dump one signal if it has changed

2
src/V3AstNodes.cpp
View File

@ -181,8 +181,6 @@ void AstVar::combineType(AstVarType type) {
// These flags get combined with the existing settings of the flags.
// We don't test varType for certain types, instead set flags since
// when we combine wires cross-hierarchy we need a union of all characteristics.
if (type == AstVarType::SUPPLY0) type = AstVarType::WIRE;
if (type == AstVarType::SUPPLY1) type = AstVarType::WIRE;
m_varType=type; // For debugging prints only
// These flags get combined with the existing settings of the flags.
if (type==AstVarType::INPUT || type==AstVarType::INOUT) {

12
src/V3AstNodes.h
View File

@ -1093,6 +1093,7 @@ private:
string m_origName; // Original name before dot addition
string m_tag; // Holds the string of the verilator tag -- used in XML output.
AstVarType m_varType; // Type of variable
AstBasicDTypeKwd m_declKwd; // Keyword at declaration time
bool m_input:1; // Input or inout
bool m_output:1; // Output or inout
bool m_tristate:1; // Inout or triwire or trireg
@ -1149,6 +1150,8 @@ public:
combineType(type);
childDTypep(dtp); // Only for parser
dtypep(NULL); // V3Width will resolve
if (dtp->basicp()) m_declKwd = dtp->basicp()->keyword();
else m_declKwd = AstBasicDTypeKwd::LOGIC;
}
AstVar(FileLine* fl, AstVarType type, const string& name, AstNodeDType* dtp)
:AstNode(fl)
@ -1157,6 +1160,8 @@ public:
combineType(type);
UASSERT(dtp,"AstVar created with no dtype");
dtypep(dtp);
if (dtp->basicp()) m_declKwd = dtp->basicp()->keyword();
else m_declKwd = AstBasicDTypeKwd::LOGIC;
}
AstVar(FileLine* fl, AstVarType type, const string& name, VFlagLogicPacked, int wantwidth)
:AstNode(fl)
@ -1164,6 +1169,7 @@ public:
init();
combineType(type);
dtypeSetLogicSized(wantwidth,wantwidth,AstNumeric::UNSIGNED);
m_declKwd = AstBasicDTypeKwd::LOGIC;
}
AstVar(FileLine* fl, AstVarType type, const string& name, VFlagBitPacked, int wantwidth)
:AstNode(fl)
@ -1171,6 +1177,7 @@ public:
init();
combineType(type);
dtypeSetLogicSized(wantwidth,wantwidth,AstNumeric::UNSIGNED);
m_declKwd = AstBasicDTypeKwd::BIT;
}
AstVar(FileLine* fl, AstVarType type, const string& name, AstVar* examplep)
:AstNode(fl)
@ -1181,6 +1188,7 @@ public:
childDTypep(examplep->childDTypep()->cloneTree(true));
}
dtypeFrom(examplep);
m_declKwd = examplep->declKwd();
}
ASTNODE_NODE_FUNCS(Var)
virtual void dump(std::ostream& str);
@ -1193,6 +1201,7 @@ public:
void varType(AstVarType type) { m_varType = type; }
void varType2Out() { m_tristate=0; m_input=0; m_output=1; }
void varType2In() { m_tristate=0; m_input=1; m_output=0; }
AstBasicDTypeKwd declKwd() const { return m_declKwd; }
string scType() const; // Return SysC type: bool, uint32_t, uint64_t, sc_bv
string cPubArgType(bool named, bool forReturn) const; // Return C /*public*/ type for argument: bool, uint32_t, uint64_t, etc.
string dpiArgType(bool named, bool forReturn) const; // Return DPI-C type for argument
@ -3354,6 +3363,7 @@ private:
VNumRange m_arrayRange; // Property of var the trace details
uint32_t m_codeInc; // Code increment
AstVarType m_varType; // Type of variable (for localparam vs. param)
AstBasicDTypeKwd m_declKwd; // Keyword at declaration time
bool m_declInput:1; // Input or inout
bool m_declOutput:1; // Output or inout
public:
@ -3368,6 +3378,7 @@ public:
m_codeInc = ((arrayRange.ranged() ? arrayRange.elements() : 1)
* valuep->dtypep()->widthWords());
m_varType = varp->varType();
m_declKwd = varp->declKwd();
m_declInput = varp->isDeclInput();
m_declOutput = varp->isDeclOutput();
}
@ -3385,6 +3396,7 @@ public:
const VNumRange& bitRange() const { return m_bitRange; }
const VNumRange& arrayRange() const { return m_arrayRange; }
AstVarType varType() const { return m_varType; }
AstBasicDTypeKwd declKwd() const { return m_declKwd; }
bool declInput() const { return m_declInput; }
bool declOutput() const { return m_declOutput; }
bool declInout() const { return m_declInput && m_declOutput; }

52
src/V3EmitC.cpp
View File

@ -2838,10 +2838,54 @@ class EmitCTrace : EmitCStmts {
putsQuoted(nodep->showname());
// Direction
if (v3Global.opt.traceFormat() == TraceFormat::FST) {
if (nodep->declInout()) puts(",VLVD_INOUT");
else if (nodep->declInput()) puts(",VLVD_IN");
else if (nodep->declOutput()) puts(",VLVD_OUT");
else puts(",VLVD_0");
// fstVarDir
if (nodep->declInout()) puts(",FST_VD_INOUT");
else if (nodep->declInput()) puts(",FST_VD_INPUT");
else if (nodep->declOutput()) puts(",FST_VD_OUTPUT");
else puts(",FST_VD_IMPLICIT");
//
// fstVarType
AstVarType vartype = nodep->varType();
AstBasicDTypeKwd kwd = nodep->declKwd();
string fstvt;
// Doubles have special decoding properties, so must indicate if a double
if (nodep->dtypep()->basicp()->isDouble()) {
if (vartype == AstVarType::GPARAM || vartype == AstVarType::LPARAM) {
fstvt = "FST_VT_VCD_REAL_PARAMETER";
} else fstvt = "FST_VT_VCD_REAL";
}
else if (vartype == AstVarType::GPARAM) fstvt = "FST_VT_VCD_PARAMETER";
else if (vartype == AstVarType::LPARAM) fstvt = "FST_VT_VCD_PARAMETER";
else if (vartype == AstVarType::SUPPLY0) fstvt = "FST_VT_VCD_SUPPLY0";
else if (vartype == AstVarType::SUPPLY1) fstvt = "FST_VT_VCD_SUPPLY1";
else if (vartype == AstVarType::TRI0) fstvt = "FST_VT_VCD_TRI0";
else if (vartype == AstVarType::TRI1) fstvt = "FST_VT_VCD_TRI1";
else if (vartype == AstVarType::TRIWIRE) fstvt = "FST_VT_VCD_TRI";
else if (vartype == AstVarType::WIRE) fstvt = "FST_VT_VCD_WIRE";
//
else if (kwd == AstBasicDTypeKwd::INTEGER) fstvt = "FST_VT_VCD_INTEGER";
else if (kwd == AstBasicDTypeKwd::BIT) fstvt = "FST_VT_SV_BIT";
else if (kwd == AstBasicDTypeKwd::LOGIC) fstvt = "FST_VT_SV_LOGIC";
else if (kwd == AstBasicDTypeKwd::INT) fstvt = "FST_VT_SV_INT";
else if (kwd == AstBasicDTypeKwd::SHORTINT) fstvt = "FST_VT_SV_SHORTINT";
else if (kwd == AstBasicDTypeKwd::LONGINT) fstvt = "FST_VT_SV_LONGINT";
else if (kwd == AstBasicDTypeKwd::BYTE) fstvt = "FST_VT_SV_BYTE";
else fstvt = "FST_VT_SV_BIT";
//
// Not currently supported
// FST_VT_VCD_EVENT
// FST_VT_VCD_PORT
// FST_VT_VCD_SHORTREAL
// FST_VT_VCD_REALTIME
// FST_VT_VCD_SPARRAY
// FST_VT_VCD_TRIAND
// FST_VT_VCD_TRIOR
// FST_VT_VCD_TRIREG
// FST_VT_VCD_WAND
// FST_VT_VCD_WOR
// FST_VT_SV_ENUM
// FST_VT_GEN_STRING
puts(","+fstvt);
}
// Range
if (nodep->arrayRange().ranged()) {

48
test_regress/t/t_trace_array_fst.out
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File diff suppressed because one or more lines are too long

50
test_regress/t/t_trace_complex_fst.out
View File

@ -1,5 +1,5 @@
$date
Tue Oct 2 18:35:11 2018
Thu Oct 4 19:33:39 2018
$end
$version
@ -9,45 +9,45 @@ $timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$var bit 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 32 " cyc $end
$var wire 2 # v_strp $end
$var wire 4 $ v_strp_strp $end
$var wire 2 % v_unip_strp $end
$var wire 2 & v_arrp $end
$var wire 4 ' v_arrp_arrp $end
$var wire 4 ( v_arrp_strp $end
$var wire 1 ) v_arru(1) $end
$var wire 1 * v_arru(2) $end
$var wire 1 + v_arru_arru(3)(1) $end
$var wire 1 , v_arru_arru(3)(2) $end
$var wire 1 - v_arru_arru(4)(1) $end
$var wire 1 . v_arru_arru(4)(2) $end
$var wire 2 / v_arru_arrp(3) $end
$var wire 2 0 v_arru_arrp(4) $end
$var wire 2 1 v_arru_strp(3) $end
$var wire 2 2 v_arru_strp(4) $end
$var integer 32 " cyc $end
$var logic 2 # v_strp $end
$var logic 4 $ v_strp_strp $end
$var logic 2 % v_unip_strp $end
$var logic 2 & v_arrp $end
$var logic 4 ' v_arrp_arrp $end
$var logic 4 ( v_arrp_strp $end
$var logic 1 ) v_arru(1) $end
$var logic 1 * v_arru(2) $end
$var logic 1 + v_arru_arru(3)(1) $end
$var logic 1 , v_arru_arru(3)(2) $end
$var logic 1 - v_arru_arru(4)(1) $end
$var logic 1 . v_arru_arru(4)(2) $end
$var logic 2 / v_arru_arrp(3) $end
$var logic 2 0 v_arru_arrp(4) $end
$var logic 2 1 v_arru_strp(3) $end
$var logic 2 2 v_arru_strp(4) $end
$var real 64 3 v_real $end
$var real 64 4 v_arr_real(0) $end
$var real 64 5 v_arr_real(1) $end
$var wire 64 6 v_str32x2 $end
$var logic 64 6 v_str32x2 $end
$scope module unnamedblk1 $end
$var wire 32 7 b $end
$var integer 32 7 b $end
$scope module unnamedblk2 $end
$var wire 32 8 a $end
$var integer 32 8 a $end
$upscope $end
$upscope $end
$scope module p2 $end
$var wire 32 9 PARAM $end
$var parameter 32 9 PARAM $end
$upscope $end
$scope module p3 $end
$var wire 32 : PARAM $end
$var parameter 32 : PARAM $end
$upscope $end
$upscope $end
$scope module $unit $end
$var wire 1 ; global_bit $end
$var bit 1 ; global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end

50
test_regress/t/t_trace_complex_params_fst.out
View File

@ -1,5 +1,5 @@
$date
Tue Oct 2 18:35:13 2018
Thu Oct 4 19:33:40 2018
$end
$version
@ -9,45 +9,45 @@ $timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$var bit 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 32 " cyc $end
$var wire 2 # v_strp $end
$var wire 4 $ v_strp_strp $end
$var wire 2 % v_unip_strp $end
$var wire 2 & v_arrp $end
$var wire 4 ' v_arrp_arrp $end
$var wire 4 ( v_arrp_strp $end
$var wire 1 ) v_arru(1) $end
$var wire 1 * v_arru(2) $end
$var wire 1 + v_arru_arru(3)(1) $end
$var wire 1 , v_arru_arru(3)(2) $end
$var wire 1 - v_arru_arru(4)(1) $end
$var wire 1 . v_arru_arru(4)(2) $end
$var wire 2 / v_arru_arrp(3) $end
$var wire 2 0 v_arru_arrp(4) $end
$var wire 2 1 v_arru_strp(3) $end
$var wire 2 2 v_arru_strp(4) $end
$var integer 32 " cyc $end
$var logic 2 # v_strp $end
$var logic 4 $ v_strp_strp $end
$var logic 2 % v_unip_strp $end
$var logic 2 & v_arrp $end
$var logic 4 ' v_arrp_arrp $end
$var logic 4 ( v_arrp_strp $end
$var logic 1 ) v_arru(1) $end
$var logic 1 * v_arru(2) $end
$var logic 1 + v_arru_arru(3)(1) $end
$var logic 1 , v_arru_arru(3)(2) $end
$var logic 1 - v_arru_arru(4)(1) $end
$var logic 1 . v_arru_arru(4)(2) $end
$var logic 2 / v_arru_arrp(3) $end
$var logic 2 0 v_arru_arrp(4) $end
$var logic 2 1 v_arru_strp(3) $end
$var logic 2 2 v_arru_strp(4) $end
$var real 64 3 v_real $end
$var real 64 4 v_arr_real(0) $end
$var real 64 5 v_arr_real(1) $end
$var wire 64 6 v_str32x2 $end
$var logic 64 6 v_str32x2 $end
$scope module unnamedblk1 $end
$var wire 32 7 b $end
$var integer 32 7 b $end
$scope module unnamedblk2 $end
$var wire 32 8 a $end
$var integer 32 8 a $end
$upscope $end
$upscope $end
$scope module p2 $end
$var wire 32 9 PARAM $end
$var parameter 32 9 PARAM $end
$upscope $end
$scope module p3 $end
$var wire 32 : PARAM $end
$var parameter 32 : PARAM $end
$upscope $end
$upscope $end
$scope module $unit $end
$var wire 1 ; global_bit $end
$var bit 1 ; global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end

74
test_regress/t/t_trace_complex_structs_fst.out
View File

@ -1,5 +1,5 @@
$date
Tue Oct 2 18:35:16 2018
Thu Oct 4 19:33:40 2018
$end
$version
@ -9,79 +9,79 @@ $timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$var bit 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 32 " cyc $end
$var integer 32 " cyc $end
$scope module v_strp $end
$var wire 1 # b1 $end
$var wire 1 $ b0 $end
$var logic 1 # b1 $end
$var logic 1 $ b0 $end
$upscope $end
$scope module v_strp_strp $end
$scope module x1 $end
$var wire 1 % b1 $end
$var wire 1 & b0 $end
$var logic 1 % b1 $end
$var logic 1 & b0 $end
$upscope $end
$scope module x0 $end
$var wire 1 ' b1 $end
$var wire 1 ( b0 $end
$var logic 1 ' b1 $end
$var logic 1 ( b0 $end
$upscope $end
$upscope $end
$scope module v_unip_strp $end
$scope module x1 $end
$var wire 1 ) b1 $end
$var wire 1 * b0 $end
$var logic 1 ) b1 $end
$var logic 1 * b0 $end
$upscope $end
$scope module x0 $end
$var wire 1 ) b1 $end
$var wire 1 * b0 $end
$var logic 1 ) b1 $end
$var logic 1 * b0 $end
$upscope $end
$upscope $end
$var wire 2 + v_arrp $end
$var wire 2 , v_arrp_arrp(3) $end
$var wire 2 - v_arrp_arrp(4) $end
$var logic 2 + v_arrp $end
$var logic 2 , v_arrp_arrp(3) $end
$var logic 2 - v_arrp_arrp(4) $end
$scope module v_arrp_strp(3) $end
$var wire 1 . b1 $end
$var wire 1 / b0 $end
$var logic 1 . b1 $end
$var logic 1 / b0 $end
$upscope $end
$scope module v_arrp_strp(4) $end
$var wire 1 0 b1 $end
$var wire 1 1 b0 $end
$var logic 1 0 b1 $end
$var logic 1 1 b0 $end
$upscope $end
$var wire 1 2 v_arru(1) $end
$var wire 1 3 v_arru(2) $end
$var wire 1 4 v_arru_arru(3)(1) $end
$var wire 1 5 v_arru_arru(3)(2) $end
$var wire 1 6 v_arru_arru(4)(1) $end
$var wire 1 7 v_arru_arru(4)(2) $end
$var wire 2 8 v_arru_arrp(3) $end
$var wire 2 9 v_arru_arrp(4) $end
$var logic 1 2 v_arru(1) $end
$var logic 1 3 v_arru(2) $end
$var logic 1 4 v_arru_arru(3)(1) $end
$var logic 1 5 v_arru_arru(3)(2) $end
$var logic 1 6 v_arru_arru(4)(1) $end
$var logic 1 7 v_arru_arru(4)(2) $end
$var logic 2 8 v_arru_arrp(3) $end
$var logic 2 9 v_arru_arrp(4) $end
$scope module v_arru_strp(3) $end
$var wire 1 : b1 $end
$var wire 1 ; b0 $end
$var logic 1 : b1 $end
$var logic 1 ; b0 $end
$upscope $end
$scope module v_arru_strp(4) $end
$var wire 1 < b1 $end
$var wire 1 = b0 $end
$var logic 1 < b1 $end
$var logic 1 = b0 $end
$upscope $end
$var real 64 > v_real $end
$var real 64 ? v_arr_real(0) $end
$var real 64 @ v_arr_real(1) $end
$scope module v_str32x2(0) $end
$var wire 32 A data $end
$var logic 32 A data $end
$upscope $end
$scope module v_str32x2(1) $end
$var wire 32 B data $end
$var logic 32 B data $end
$upscope $end
$scope module unnamedblk1 $end
$var wire 32 C b $end
$var integer 32 C b $end
$scope module unnamedblk2 $end
$var wire 32 D a $end
$var integer 32 D a $end
$upscope $end
$upscope $end
$upscope $end
$scope module $unit $end
$var wire 1 E global_bit $end
$var bit 1 E global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end

1265
test_regress/t/t_trace_fst.out
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File diff suppressed because it is too large Load Diff

20
test_regress/t/t_trace_fst.v
View File

@ -14,6 +14,26 @@ module t (/*AUTOARG*/
reg rstn;
output [4:0] state;
parameter real fst_gparam_real = 1.23;
localparam real fst_lparam_real = 4.56;
real fst_real = 1.23;
integer fst_integer;
bit fst_bit;
logic fst_logic;
int fst_int;
shortint fst_shortint;
longint fst_longint;
byte fst_byte;
parameter fst_parameter = 123;
localparam fst_lparam = 456;
supply0 fst_supply0;
supply1 fst_supply1;
tri0 fst_tri0;
tri1 fst_tri1;
tri fst_tri;
wire fst_wire;
Test test (/*AUTOINST*/
// Outputs
.state (state[4:0]),

12
test_regress/t/t_trace_packed_struct_fst.out
View File

@ -1,5 +1,5 @@
$date
Tue Oct 2 18:35:19 2018
Thu Oct 4 19:33:41 2018
$end
$version
@ -9,13 +9,13 @@ $timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$var bit 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 32 " cnt $end
$var wire 96 # v(0) $end
$var wire 96 $ v(1) $end
$var wire 96 % v(2) $end
$var int 32 " cnt $end
$var parameter 96 # v(0) $end
$var parameter 96 $ v(1) $end
$var parameter 96 % v(2) $end
$upscope $end
$upscope $end
$enddefinitions $end