luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 01:54:01 +02:00
Code Issues Packages Projects Releases Wiki Activity

Do not create aliases for forced port signals (#5105)

Browse Source 
+ don't remove forced signals in V3Const and Dfg

Fixes #5062
This commit is contained in:
Geza Lore
2024-05-10 18:19:51 +01:00
committed by GitHub
parent 45eb5b8a5c
commit cf111d2e1f
16 changed files with 207 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/V3DfgPasses.cpp
+2 -2
View File
@@ -165,8 +165,8 @@ void V3DfgPasses::inlineVars(DfgGraph& dfg) {
const AstVar* const astVarp = driverVarp->varp();
// If driven from a SystemC variable
if (astVarp->isSc()) continue;
// If the variable is forceable
if (astVarp->isForceable()) continue;
// If the variable is forced
if (astVarp->isForced()) continue;
}
varp->forEachSinkEdge([=](DfgEdge& edge) { edge.relinkSource(driverp); });