luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-06 18:13:50 +02:00
Code Issues Packages Projects Releases Wiki Activity

Do not create aliases for forced port signals (#5105)

Browse Source 
+ don't remove forced signals in V3Const and Dfg

Fixes #5062
This commit is contained in:
Geza Lore
2024-05-10 18:19:51 +01:00
committed by GitHub
parent 45eb5b8a5c
commit cf111d2e1f
16 changed files with 207 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/V3Const.cpp
+3 -2
View File
@@ -3071,8 +3071,9 @@ class ConstVisitor final : public VNVisitor {
&& varrefp // Don't do messes with BITREFs/ARRAYREFs
&& !varrefp->varp()->hasStrengthAssignment() // Strengths are resolved in V3Tristate
&& !varrefp->varp()->valuep() // Not already constified
&& !varrefp->varScopep()) { // Not scoped (or each scope may have different initial
// value)
&& !varrefp->varScopep() // Not scoped (or each scope may have different initial val.)
&& !varrefp->varp()->isForced() // Not forced (not really a constant)
) {
// ASSIGNW (VARREF, const) -> INITIAL ( ASSIGN (VARREF, const) )
UINFO(4, "constAssignW " << nodep << endl);
// Make a initial assignment