mirror of
https://github.com/verilator/verilator.git
synced 2026-10-06 01:54:01 +02:00
Generate AstNode accessors via astgen
Introduce the @astgen directives parsed by astgen, currently used for the generation child node (operand) accessors. Please see the updated internal documentation for details.
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+15
-15
@@ -294,15 +294,15 @@ private:
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UASSERT_OBJ(exprconstp || exprvarrefp, nodep,
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"Unknown interconnect type; pinReconnectSimple should have cleared up");
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if (exprconstp) {
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m_modp->addStmtp(new AstAssignW(flp, new AstVarRef(flp, nodep, VAccess::WRITE),
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exprconstp->cloneTree(false)));
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m_modp->addStmtsp(new AstAssignW(flp, new AstVarRef(flp, nodep, VAccess::WRITE),
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exprconstp->cloneTree(false)));
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} else if (nodep->user3()) {
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// Public variable at the lower module end - we need to make sure we propagate
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// the logic changes up and down; if we aliased, we might
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// remove the change detection on the output variable.
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UINFO(9, "public pin assign: " << exprvarrefp << endl);
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UASSERT_OBJ(!nodep->isNonOutput(), nodep, "Outputs only - inputs use AssignAlias");
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m_modp->addStmtp(
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m_modp->addStmtsp(
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new AstAssignW(flp, new AstVarRef(flp, exprvarrefp->varp(), VAccess::WRITE),
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new AstVarRef(flp, nodep, VAccess::READ)));
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} else if (nodep->isSigPublic() && VN_IS(nodep->dtypep(), UnpackArrayDType)) {
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@@ -310,11 +310,11 @@ private:
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// instead of aliased, because otherwise it will pass V3Slice and invalid
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// code will be emitted.
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UINFO(9, "assign to public and unpacked: " << nodep << endl);
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m_modp->addStmtp(
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m_modp->addStmtsp(
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new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
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new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
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} else if (nodep->isIfaceRef()) {
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m_modp->addStmtp(
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m_modp->addStmtsp(
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new AstAssignVarScope(flp, new AstVarRef(flp, nodep, VAccess::WRITE),
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new AstVarRef(flp, exprvarrefp->varp(), VAccess::READ)));
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FileLine* const flbp = exprvarrefp->varp()->fileline();
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@@ -323,7 +323,7 @@ private:
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} else {
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// Do to inlining child's variable now within the same
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// module, so a AstVarRef not AstVarXRef below
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m_modp->addStmtp(
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m_modp->addStmtsp(
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new AstAssignAlias(flp, new AstVarRef(flp, nodep, VAccess::WRITE),
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new AstVarRef(flp, exprvarrefp->varp(), VAccess::READ)));
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FileLine* const flbp = exprvarrefp->varp()->fileline();
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@@ -423,16 +423,16 @@ private:
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// If there's a %m in the display text, we add a special node that will contain the name()
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// Similar code in V3Begin
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// To keep correct visual order, must add before other Text's
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AstNode* afterp = nodep->scopeAttrp();
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AstText* afterp = nodep->scopeAttrp();
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if (afterp) afterp->unlinkFrBackWithNext();
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nodep->scopeAttrp(
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nodep->addScopeAttrp(
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new AstText{nodep->fileline(), std::string{"__DOT__"} + m_cellp->name()});
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if (afterp) nodep->scopeAttrp(afterp);
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if (afterp) nodep->addScopeAttrp(afterp);
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afterp = nodep->scopeEntrp();
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if (afterp) afterp->unlinkFrBackWithNext();
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nodep->scopeEntrp(
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nodep->addScopeEntrp(
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new AstText{nodep->fileline(), std::string{"__DOT__"} + m_cellp->name()});
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if (afterp) nodep->scopeEntrp(afterp);
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if (afterp) nodep->addScopeEntrp(afterp);
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iterateChildren(nodep);
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}
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void visit(AstCoverDecl* nodep) override {
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@@ -566,7 +566,7 @@ private:
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// Move statements under the module we are inlining into
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if (AstNode* const stmtsp = newmodp->stmtsp()) {
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stmtsp->unlinkFrBackWithNext();
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m_modp->addStmtp(stmtsp);
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m_modp->addStmtsp(stmtsp);
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}
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// Clear any leftover ports, etc
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VL_DO_DANGLING(newmodp->deleteTree(), newmodp);
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@@ -649,7 +649,7 @@ private:
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}
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if (VN_IS(nodep->modp(), Iface)) {
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nodep->addIntfRefp(new AstIntfRef{nodep->fileline(), m_scope});
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nodep->addIntfRefsp(new AstIntfRef{nodep->fileline(), m_scope});
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}
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{
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AstNodeModule* const modp = nodep->modp();
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@@ -666,7 +666,7 @@ private:
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if ((cellp = VN_CAST(fromVarp->user1p(), Cell)) || (cellp = irdtp->cellp())) {
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varp->user1p(cellp);
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const string alias = m_scope + "__DOT__" + pinp->name();
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cellp->addIntfRefp(new AstIntfRef(pinp->fileline(), alias));
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cellp->addIntfRefsp(new AstIntfRef(pinp->fileline(), alias));
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}
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}
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@@ -695,7 +695,7 @@ private:
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string alias;
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if (!m_scope.empty()) alias = m_scope + "__DOT__";
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alias += varlp->name();
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cellp->addIntfRefp(new AstIntfRef(varlp->fileline(), alias));
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cellp->addIntfRefsp(new AstIntfRef(varlp->fileline(), alias));
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}
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//--------------------
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void visit(AstNodeMath*) override {} // Accelerate
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