luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-09-01 10:27:04 +02:00
Code Issues Packages Projects Releases Wiki Activity

Generate AstNode accessors via astgen

Browse Source 
Introduce the @astgen directives parsed by astgen, currently used for
the generation child node (operand) accessors. Please see the updated
internal documentation for details.
This commit is contained in:
Geza Lore
2022-09-21 13:56:03 +01:00
parent 0a8cfb8d2c
commit ce03293128
70 changed files with 1386 additions and 1530 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/V3Delayed.cpp
+4 -4
View File
@@ -153,13 +153,13 @@ private:
varp = new AstVar(oldvarscp->fileline(), VVarType::BLOCKTEMP, name,
VFlagBitPacked(), width);
}
addmodp->addStmtp(varp);
addmodp->addStmtsp(varp);
m_modVarMap.emplace(std::make_pair(addmodp, name), varp);
}
AstVarScope* const varscp
= new AstVarScope(oldvarscp->fileline(), oldvarscp->scopep(), varp);
oldvarscp->scopep()->addVarp(varscp);
oldvarscp->scopep()->addVarsp(varscp);
return varscp;
}
@@ -356,11 +356,11 @@ private:
postLogicp = new AstIf(nodep->fileline(),
new AstVarRef(nodep->fileline(), setvscp, VAccess::READ));
UINFO(9, " Created " << postLogicp << endl);
finalp->addStmtp(postLogicp);
finalp->addStmtsp(postLogicp);
finalp->user3p(setvscp); // Remember IF's vset variable
finalp->user4p(postLogicp); // and the associated IF, as we may be able to reuse it
}
postLogicp->addIfsp(new AstAssign(nodep->fileline(), selectsp, valreadp));
postLogicp->addThensp(new AstAssign(nodep->fileline(), selectsp, valreadp));
return newlhsp;
}