Fixes #7658
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@ -318,7 +318,7 @@ public:
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bool firedAtInitialization = false;
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for (AstSenItem* senItemp = senTreep->sensesp(); senItemp;
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senItemp = VN_AS(senItemp->nextp(), SenItem)) {
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const auto& pair = createTerm(senItemp);
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const auto& pair = build(senItemp);
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if (AstNodeExpr* termp = pair.first) {
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resultp = resultp ? new AstOr{flp, resultp, termp} : termp;
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firedAtInitialization |= pair.second;
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary", "--timing"])
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test.execute()
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test.passes()
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@ -0,0 +1,29 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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class monitor;
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bit clk, enable, fired;
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task run();
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forever @(posedge clk iff enable) fired = 1;
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endtask
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endclass
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module t;
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monitor mon = new;
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always #5 mon.clk = ~mon.clk;
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initial begin
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fork mon.run(); join_none
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repeat(4) @(posedge mon.clk);
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if (mon.fired !== 0) begin $display("FAIL: fired before iff guard satisfied"); $stop; end
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mon.enable = 1;
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repeat (2) @(posedge mon.clk);
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if (mon.fired !== 1) begin $display("FAIL: did not fire when guard true"); $stop; end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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