tests: Fix bogus set of output.

2014-03-14 20:19:56 -04:00 · 2014-03-14 20:19:56 -04:00 · ccb6545c32
parent d146dbc9d7
commit ccb6545c32
1 changed files with 1 additions and 1 deletions
--- a/test_regress/t/t_lint_implicit_port.v
+++ b/test_regress/t/t_lint_implicit_port.v
@ -13,7 +13,7 @@ module t (/*AUTOARG*/

   read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) );
   set  s (.clk(clk), .enable(implicit_write));
-   set  u (.clk(clk), .enable(~implicit_also));
+   read u (.clk(clk), .data(~implicit_also));

 endmodule