Merge fdeccdc45e into 397e64903c
This commit is contained in:
em2machine
GitHub
commit
cbd79e5f16
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@ -189,6 +189,7 @@ set(HEADERS
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V3Tristate.h
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V3Udp.h
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V3Undriven.h
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V3UndrivenCapture.h
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V3UniqueNames.h
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V3Unknown.h
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V3Unroll.h
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@ -358,6 +359,7 @@ set(COMMON_SOURCES
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V3Tristate.cpp
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V3Udp.cpp
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V3Undriven.cpp
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V3UndrivenCapture.cpp
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V3Unknown.cpp
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V3Unroll.cpp
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V3UnrollGen.cpp
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@ -341,6 +341,7 @@ RAW_OBJS_PCH_ASTNOMT = \
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V3Tristate.o \
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V3Udp.o \
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V3Undriven.o \
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V3UndrivenCapture.o \
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V3Unknown.o \
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V3Unroll.o \
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V3UnrollGen.o \
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@ -28,6 +28,7 @@
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#include "V3Undriven.h"
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#include "V3Stats.h"
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#include "V3UndrivenCapture.h"
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#include <vector>
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@ -51,6 +52,9 @@ class UndrivenVarEntry final {
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const FileLine* m_nodeFileLinep = nullptr; // File line of varref if driven, else nullptr
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bool m_underGen = false; // Under a generate
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const AstNodeFTaskRef* m_callNodep
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= nullptr; // Call node if driven via writeSummary, else nullptr
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enum : uint8_t { FLAG_USED = 0, FLAG_DRIVEN = 1, FLAG_DRIVEN_ALWCOMB = 2, FLAGS_PER_BIT = 3 };
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public:
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@ -278,6 +282,12 @@ public:
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}
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}
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}
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void drivenViaCall(const AstNodeFTaskRef* nodep) {
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drivenWhole();
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if (!m_callNodep) { m_callNodep = nodep; }
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}
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const AstNodeFTaskRef* callNodep() const { return m_callNodep; }
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};
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//######################################################################
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@ -304,6 +314,8 @@ class UndrivenVisitor final : public VNVisitorConst {
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const AstAlways* m_alwaysp = nullptr; // Current always of either type
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const AstAlways* m_alwaysCombp = nullptr; // Current always if combo, otherwise nullptr
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V3UndrivenCapture* const m_capturep = nullptr; // Capture object. 'nullptr' if disabled.
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// METHODS
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UndrivenVarEntry* getEntryp(AstVar* nodep, int which_user) {
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@ -420,6 +432,16 @@ class UndrivenVisitor final : public VNVisitorConst {
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<< " (IEEE 1800-2023 13.5): " << nodep->prettyNameQ());
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}
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}
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// If writeSummary is enabled, task/function definitions are treated as non-executed.
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// Their effects are applied at call sites via writeSummary(), so don't let definition
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// traversal create phantom "other writes" for MULTIDRIVEN.
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if (m_taskp && !m_alwaysp && !m_inContAssign && !m_inInitialStatic && !m_inBBox
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&& !m_taskp->dpiExport()) {
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AstVar* const retVarp = VN_CAST(m_taskp->fvarp(), Var);
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if (!retVarp || nodep->varp() != retVarp) return;
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}
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for (int usr = 1; usr < (m_alwaysCombp ? 3 : 2); ++usr) {
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UndrivenVarEntry* const entryp = getEntryp(nodep->varp(), usr);
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const bool fdrv = nodep->access().isWriteOrRW()
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@ -432,7 +454,12 @@ class UndrivenVisitor final : public VNVisitorConst {
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if (entryp->isDrivenWhole() && !m_inBBox && !VN_IS(nodep, VarXRef)
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&& !VN_IS(nodep->dtypep()->skipRefp(), UnpackArrayDType)
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&& nodep->fileline() != entryp->getNodeFileLinep() && !entryp->isUnderGen()
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&& entryp->getNodep()) {
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&& (entryp->getNodep() || entryp->callNodep())) {
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const AstNode* const otherWritep
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= entryp->getNodep() ? static_cast<const AstNode*>(entryp->getNodep())
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: entryp->callNodep();
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if (m_alwaysCombp
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&& (!entryp->isDrivenAlwaysCombWhole()
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|| (m_alwaysCombp != entryp->getAlwCombp()
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@ -443,20 +470,18 @@ class UndrivenVisitor final : public VNVisitorConst {
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<< " (IEEE 1800-2023 9.2.2.2): " << nodep->prettyNameQ() << '\n'
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<< nodep->warnOther() << '\n'
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<< nodep->warnContextPrimary() << '\n'
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<< entryp->getNodep()->warnOther()
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<< "... Location of other write\n"
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<< entryp->getNodep()->warnContextSecondary());
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<< otherWritep->warnOther() << "... Location of other write\n"
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<< otherWritep->warnContextSecondary());
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}
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if (!m_alwaysCombp && entryp->isDrivenAlwaysCombWhole()) {
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nodep->v3warn(MULTIDRIVEN,
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"Variable also written to in always_comb"
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<< " (IEEE 1800-2023 9.2.2.2): " << nodep->prettyNameQ()
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<< '\n'
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<< nodep->warnOther() << '\n'
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<< nodep->warnContextPrimary() << '\n'
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<< entryp->getNodep()->warnOther()
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<< "... Location of always_comb write\n"
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<< entryp->getNodep()->warnContextSecondary());
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nodep->v3warn(MULTIDRIVEN, "Variable also written to in always_comb"
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<< " (IEEE 1800-2023 9.2.2.2): "
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<< nodep->prettyNameQ() << '\n'
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<< nodep->warnOther() << '\n'
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<< nodep->warnContextPrimary() << '\n'
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<< otherWritep->warnOther()
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<< "... Location of always_comb write\n"
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<< otherWritep->warnContextSecondary());
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}
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}
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entryp->drivenWhole(nodep, nodep->fileline());
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@ -523,10 +548,39 @@ class UndrivenVisitor final : public VNVisitorConst {
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iterateChildrenConst(nodep);
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if (nodep->keyword() == VAlwaysKwd::ALWAYS_COMB) UINFO(9, " Done " << nodep);
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}
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void visit(AstNodeFTaskRef* nodep) override {
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VL_RESTORER(m_inFTaskRef);
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m_inFTaskRef = true;
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iterateChildrenConst(nodep);
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if (!m_capturep) return;
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// If writeSummary is enabled, task/function definitions are treated as non-executed.
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// Do not apply writeSummary at calls inside a task definition, or they will look like
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// independent drivers (phantom MULTIDRIVEN). Did the lambda on purpose - lessen chance of
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// screwup in future edits.
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const auto inExecutedContext = [this]() {
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return !(m_taskp && !m_alwaysp && !m_inContAssign && !m_inInitialStatic && !m_inBBox
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&& !m_taskp->dpiExport());
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};
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if (!inExecutedContext()) return;
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AstNodeFTask* const calleep = nodep->taskp();
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if (!calleep) return;
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const auto& vars = m_capturep->writeSummary(calleep);
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for (AstVar* const varp : vars) {
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for (int usr = 1; usr < (m_alwaysCombp ? 3 : 2); ++usr) {
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UndrivenVarEntry* const entryp = getEntryp(varp, usr);
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entryp->drivenViaCall(nodep);
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if (m_alwaysCombp)
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entryp->drivenAlwaysCombWhole(m_alwaysCombp, m_alwaysCombp->fileline());
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}
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}
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}
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void visit(AstNodeFTask* nodep) override {
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@ -556,7 +610,11 @@ class UndrivenVisitor final : public VNVisitorConst {
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public:
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// CONSTRUCTORS
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explicit UndrivenVisitor(AstNetlist* nodep) { iterateConst(nodep); }
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explicit UndrivenVisitor(AstNetlist* nodep, V3UndrivenCapture* capturep)
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: m_capturep{capturep} {
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iterateConst(nodep);
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}
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~UndrivenVisitor() override {
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for (UndrivenVarEntry* ip : m_entryps[1]) ip->reportViolations();
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for (int usr = 1; usr < 3; ++usr) {
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@ -570,6 +628,9 @@ public:
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void V3Undriven::undrivenAll(AstNetlist* nodep) {
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UINFO(2, __FUNCTION__ << ":");
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{ UndrivenVisitor{nodep}; }
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V3UndrivenCapture capture{nodep};
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UndrivenVisitor{nodep, &capture};
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if (v3Global.opt.stats()) V3Stats::statsStage("undriven");
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}
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@ -0,0 +1,212 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Capture task/function write summaries for undriven checks
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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// Copyright 2003-2025 by Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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#include "V3UndrivenCapture.h"
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#include "V3Error.h"
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#include "V3Global.h"
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VL_DEFINE_DEBUG_FUNCTIONS;
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namespace {
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struct Stats final {
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uint64_t ftasks = 0;
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uint64_t varWrites = 0;
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uint64_t callEdges = 0;
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} g_stats;
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static std::string taskNameQ(const AstNodeFTask* taskp) {
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if (!taskp) return "<null>";
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return taskp->prettyNameQ();
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}
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class CaptureVisitor final : public VNVisitorConst {
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V3UndrivenCapture& m_cap;
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const AstNodeFTask* m_curTaskp = nullptr;
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static void iterateListConst(VNVisitorConst& v, AstNode* nodep) {
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for (AstNode* np = nodep; np; np = np->nextp()) np->accept(v);
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}
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public:
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explicit CaptureVisitor(V3UndrivenCapture& cap, AstNetlist* netlistp)
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: m_cap{cap} {
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iterateConst(netlistp);
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}
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private:
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// Visit a task/function definition and collect direct writes and direct callees.
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void visit(AstNodeFTask* nodep) override {
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VL_RESTORER(m_curTaskp);
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m_curTaskp = nodep;
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++g_stats.ftasks;
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UINFO(9, "undriven capture enter ftask " << nodep << " " << nodep->prettyNameQ());
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m_cap.noteTask(nodep);
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iterateListConst(*this, nodep->stmtsp());
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}
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void visit(AstNodeVarRef* nodep) override {
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if (m_curTaskp && nodep->access().isWriteOrRW()) {
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++g_stats.varWrites;
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UINFO(9, "undriven capture direct write in " << taskNameQ(m_curTaskp)
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<< " var=" << nodep->varp()->prettyNameQ()
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<< " at " << nodep->fileline());
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m_cap.noteDirectWrite(m_curTaskp, nodep->varp());
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}
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iterateChildrenConst(nodep);
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}
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void visit(AstNodeFTaskRef* nodep) override {
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// Record the call edge if resolved
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if (m_curTaskp) {
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if (AstNodeFTask* const calleep = nodep->taskp()) {
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++g_stats.callEdges;
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UINFO(9, "undriven capture call edge " << taskNameQ(m_curTaskp) << " -> "
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<< taskNameQ(calleep));
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m_cap.noteCallEdge(m_curTaskp, calleep);
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} else {
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UINFO(9, "undriven capture unresolved call in " << taskNameQ(m_curTaskp)
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<< " name=" << nodep->name());
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}
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}
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iterateChildrenConst(nodep); // still scan pins/args
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}
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void visit(AstNode* nodep) override { iterateChildrenConst(nodep); }
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};
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} // namespace
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V3UndrivenCapture::V3UndrivenCapture(AstNetlist* netlistp) {
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gather(netlistp);
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// Compute summaries for all tasks
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for (const auto& kv : m_info) (void)computeWriteSummary(kv.first);
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// Release the filter memory
|
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for (auto& kv : m_info) {
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kv.second.calleesSet.clear();
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kv.second.calleesSet.rehash(0);
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kv.second.directWritesSet.clear();
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kv.second.directWritesSet.rehash(0);
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}
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UINFO(9, "undriven capture stats ftasks="
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<< g_stats.ftasks << " varWrites=" << g_stats.varWrites
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<< " callEdges=" << g_stats.callEdges << " uniqueTasks=" << m_info.size());
|
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}
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void V3UndrivenCapture::gather(AstNetlist* netlistp) {
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// Walk netlist and populate m_info with direct writes + call edges
|
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CaptureVisitor{*this, netlistp};
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}
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const V3UndrivenCapture::FTaskInfo* V3UndrivenCapture::find(const AstNodeFTask* taskp) const {
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const auto it = m_info.find(taskp);
|
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if (it == m_info.end()) return nullptr;
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return &it->second;
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}
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const std::vector<AstVar*>& V3UndrivenCapture::writeSummary(const AstNodeFTask* taskp) {
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// Ensure entry exists even if empty
|
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(void)m_info[taskp];
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return computeWriteSummary(taskp);
|
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}
|
||||
|
||||
const std::vector<AstVar*>& V3UndrivenCapture::computeWriteSummary(const AstNodeFTask* taskp) {
|
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FTaskInfo& info = m_info[taskp];
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|
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if (info.state == State::DONE) {
|
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UINFO(9, "undriven capture writeSummary cached size=" << info.writeSummary.size()
|
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<< " for " << taskNameQ(taskp));
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return info.writeSummary;
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}
|
||||
if (info.state == State::VISITING) {
|
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UINFO(9, "undriven capture recursion detected at "
|
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<< taskNameQ(taskp)
|
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<< " returning directWrites size=" << info.directWrites.size());
|
||||
// Cycle detected. return directWrites only to guarantee termination.
|
||||
if (info.writeSummary.empty()) info.writeSummary = info.directWrites;
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return info.writeSummary;
|
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}
|
||||
|
||||
info.state = State::VISITING;
|
||||
|
||||
info.writeSummary.clear();
|
||||
|
||||
// Prevent duplicates across all sources that can contribute to a write summary (direct writes
|
||||
// and call chains)
|
||||
std::unordered_set<AstVar*> seen;
|
||||
|
||||
// Simple lambda for filtering duplicates
|
||||
auto addVar = [&](AstVar* v) {
|
||||
if (seen.insert(v).second) info.writeSummary.push_back(v);
|
||||
};
|
||||
|
||||
// Start with direct writes
|
||||
for (AstVar* v : info.directWrites) addVar(v);
|
||||
|
||||
// Add callee summaries
|
||||
for (const AstNodeFTask* calleep : info.callees) {
|
||||
if (m_info.find(calleep) == m_info.end()) continue;
|
||||
const std::vector<AstVar*>& sub = computeWriteSummary(calleep);
|
||||
for (AstVar* v : sub) addVar(v);
|
||||
}
|
||||
|
||||
UINFO(9, "undriven capture writeSummary computed size=" << info.writeSummary.size() << " for "
|
||||
<< taskNameQ(taskp));
|
||||
|
||||
// We are done, so set the m_info state correctly and return the vector of variables
|
||||
info.state = State::DONE;
|
||||
return info.writeSummary;
|
||||
}
|
||||
|
||||
void V3UndrivenCapture::noteTask(const AstNodeFTask* taskp) { (void)m_info[taskp]; }
|
||||
|
||||
void V3UndrivenCapture::noteDirectWrite(const AstNodeFTask* taskp, AstVar* varp) {
|
||||
FTaskInfo& info = m_info[taskp];
|
||||
|
||||
// Exclude function return variable (not an externally visible side-effect)
|
||||
AstVar* const retVarp = VN_CAST(taskp->fvarp(), Var);
|
||||
if (retVarp && varp == retVarp) return;
|
||||
|
||||
// Filter out duplicates.
|
||||
if (info.directWritesSet.insert(varp).second) { info.directWrites.push_back(varp); }
|
||||
}
|
||||
|
||||
void V3UndrivenCapture::noteCallEdge(const AstNodeFTask* callerp, const AstNodeFTask* calleep) {
|
||||
FTaskInfo& callerInfo = m_info[callerp];
|
||||
// Prevents duplicate entries from being appended, if calleep already exists then insert will
|
||||
// return false, and then is not inserted into the callees vector.
|
||||
if (callerInfo.calleesSet.insert(calleep).second) { callerInfo.callees.push_back(calleep); }
|
||||
// Ensure callee entry exists, if already exists then this is a no-op. unordered_map<> so
|
||||
// cheap.
|
||||
(void)m_info[calleep];
|
||||
}
|
||||
|
||||
void V3UndrivenCapture::debugDumpTask(const AstNodeFTask* taskp, int level) const {
|
||||
const auto* const infop = find(taskp);
|
||||
if (!infop) {
|
||||
UINFO(level, "undriven capture no entry for task " << taskp);
|
||||
return;
|
||||
}
|
||||
UINFO(level, "undriven capture dump task " << taskp << " " << taskp->prettyNameQ()
|
||||
<< " directWrites=" << infop->directWrites.size()
|
||||
<< " callees=" << infop->callees.size()
|
||||
<< " writeSummary=" << infop->writeSummary.size());
|
||||
}
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
// -*- mode: C++; c-file-style: "cc-mode" -*-
|
||||
//*************************************************************************
|
||||
// DESCRIPTION: Verilator: Capture task/function write summaries for undriven checks
|
||||
//
|
||||
// Code available from: https://verilator.org
|
||||
//
|
||||
//*************************************************************************
|
||||
//
|
||||
// Copyright 2003-2025 by Wilson Snyder. This program is free software; you
|
||||
// can redistribute it and/or modify it under the terms of either the GNU
|
||||
// Lesser General Public License Version 3 or the Perl Artistic License
|
||||
// Version 2.0.
|
||||
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
//
|
||||
//*************************************************************************
|
||||
|
||||
//*************************************************************************
|
||||
//
|
||||
// Capture task/function write summaries for multidriven checks.
|
||||
// Per-task/function capture info keyed by resolved AstNodeFTask* identity (FTask = function or
|
||||
// task). This is our 'graph' of tasks/functions. Each node has a list of direct callees and
|
||||
// a list of variables written in the function body. There are methods to dedup after walking the
|
||||
// tree. V3Undriven then uses the writeSummary for multidriven checks - i.e. it treats writes (side
|
||||
// effects) inside subroutines as part of the caller's process.
|
||||
//
|
||||
//*************************************************************************
|
||||
|
||||
#ifndef VERILATOR_V3UNDRIVENCAPTURE_H_
|
||||
#define VERILATOR_V3UNDRIVENCAPTURE_H_
|
||||
|
||||
#include "config_build.h"
|
||||
|
||||
#include "V3Ast.h"
|
||||
|
||||
#include <unordered_map>
|
||||
#include <unordered_set>
|
||||
#include <vector>
|
||||
|
||||
class AstNetlist;
|
||||
|
||||
class V3UndrivenCapture final {
|
||||
public:
|
||||
// DFS computation state for writeSummary propagation.
|
||||
// UNVISITED: write summary not computed yet
|
||||
// VISITING: currently computing on the call stack - used to detect cycles
|
||||
// DONE: write summary computed
|
||||
enum class State : uint8_t { UNVISITED, VISITING, DONE };
|
||||
|
||||
struct FTaskInfo final {
|
||||
// Variables written directly in this task/function body (iteration order)
|
||||
std::vector<AstVar*> directWrites;
|
||||
// Direct resolved callees from this task/function body (iteration order)
|
||||
std::vector<const AstNodeFTask*> callees;
|
||||
// 'Write through write' writeSummary for the given task/function. Meaning ultimately
|
||||
// everything that this function/task writes to.
|
||||
std::vector<AstVar*> writeSummary;
|
||||
// State for writeSummary computation.
|
||||
State state = State::UNVISITED;
|
||||
// This is used to test whether weve already recorded a callee. Used to 'filter' on insert
|
||||
// versus sorting at the end.
|
||||
std::unordered_set<const AstNodeFTask*> calleesSet;
|
||||
// This is used to test whether weve already recorded a direct write. Used to 'filter' on
|
||||
// insert versus sorting at the end.
|
||||
std::unordered_set<AstVar*> directWritesSet;
|
||||
};
|
||||
|
||||
private:
|
||||
// Per-task/function capture info keyed by resolved AstNodeFTask* identity (FTask = function or
|
||||
// task). This is our 'graph' of tasks/functions. Each node has a list of direct callees and
|
||||
// a list of variables written in the function body. There are methods to remove duplicates
|
||||
// otherwise this could explode.
|
||||
std::unordered_map<const AstNodeFTask*, FTaskInfo> m_info;
|
||||
|
||||
// Collect direct writes and call edges for all tasks/functions. Run one time when
|
||||
// UndrivenCapture is created. This runs the visitor over the tree.
|
||||
void gather(AstNetlist* netlistp);
|
||||
// Compute (and cache) 'write through write' writeSummary for the given task/function.
|
||||
const std::vector<AstVar*>& computeWriteSummary(const AstNodeFTask* taskp);
|
||||
|
||||
public:
|
||||
// Build capture database and precompute writeSummary for all discovered tasks/functions.
|
||||
explicit V3UndrivenCapture(AstNetlist* netlistp);
|
||||
|
||||
// Lookup task/function capture info (nullptr if unknown). This is currently only used for the
|
||||
// debug helper.
|
||||
const FTaskInfo* find(const AstNodeFTask* taskp) const;
|
||||
// Get write through write through write, etc (call chain) writeSummary for a task/function
|
||||
// (creates empty entry if needed). This returns a vector of variables that a particular
|
||||
// task/function writes to, including all variables written by functions called by this
|
||||
// task/function, and so on.
|
||||
const std::vector<AstVar*>& writeSummary(const AstNodeFTask* taskp);
|
||||
|
||||
// Used by the capture visitor to record information about tasks/functions and their statements
|
||||
// and callees. noteTask() makes sure there is an entry for the given taskp.
|
||||
void noteTask(const AstNodeFTask* taskp);
|
||||
// Inside the body of taskp there is a write to variable varp
|
||||
void noteDirectWrite(const AstNodeFTask* taskp, AstVar* varp);
|
||||
// Inside the body of callerp there is a call to calleep, this is needed so we can create a
|
||||
// summary that includes all variables written by functions called by this task/function, and
|
||||
// so on.
|
||||
void noteCallEdge(const AstNodeFTask* callerp, const AstNodeFTask* calleep);
|
||||
|
||||
// Dump one task's summary for debugging. leaving this in, in case need to debug future
|
||||
// functionality.
|
||||
void debugDumpTask(const AstNodeFTask* taskp, int level = 9) const;
|
||||
};
|
||||
|
||||
#endif // VERILATOR_V3UNDRIVENCAPTURE_H_
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
%Warning-MULTIDRIVEN: t/t_lint_multidriven_taskcall_bad.v:28:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out'
|
||||
: ... note: In instance 't'
|
||||
t/t_lint_multidriven_taskcall_bad.v:28:15:
|
||||
28 | if (sel2) out = 1'b1;
|
||||
| ^~~
|
||||
t/t_lint_multidriven_taskcall_bad.v:20:5: ... Location of other write
|
||||
20 | out = 1'b0;
|
||||
| ^~~
|
||||
... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest
|
||||
... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
|
||||
%Error: Exiting due to
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('linter')
|
||||
|
||||
test.lint(fails=True, expect_filename=test.golden_filename)
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (
|
||||
input logic sel,
|
||||
input logic sel2,
|
||||
input logic d,
|
||||
output logic out
|
||||
);
|
||||
|
||||
task automatic do_stuff(input logic din);
|
||||
out = din;
|
||||
endtask
|
||||
|
||||
// Driver #1 (via task call)
|
||||
always_comb begin
|
||||
out = 1'b0;
|
||||
if (sel) do_stuff(d);
|
||||
end
|
||||
|
||||
// Driver #2 (separate process)
|
||||
// I only want the MULTIDRIVEN.
|
||||
/* verilator lint_off LATCH */
|
||||
always_comb begin
|
||||
if (sel2) out = 1'b1;
|
||||
end
|
||||
/* verilator lint_on LATCH */
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,284 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// Consolidated class-based task/function multidriven tests
|
||||
// (formerly t_multidriven_class{0,1,2,3,4,f0,f1}.v)
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// class0: class task writes through ref argument (direct assignment + class task in same always_comb)
|
||||
|
||||
class C0;
|
||||
task automatic set1(ref logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
task automatic set0(ref logic q);
|
||||
q = 1'b0;
|
||||
endtask
|
||||
endclass
|
||||
|
||||
module class0 #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
C0 c;
|
||||
|
||||
initial c = new;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
c.set1(l0);
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// class1: class task chain - nested method calls write through ref in same always_comb
|
||||
|
||||
class C1;
|
||||
task automatic inner(inout logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
task automatic outer(inout logic q);
|
||||
inner(q);
|
||||
endtask
|
||||
endclass
|
||||
|
||||
module class1 #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
C1 c;
|
||||
|
||||
initial c = new;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
c.outer(l0);
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// class2: class handle passed through module port - class method writes through ref
|
||||
|
||||
class C2;
|
||||
task automatic set1(ref logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
endclass
|
||||
|
||||
module class2 #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
,C2 c
|
||||
);
|
||||
|
||||
logic l0;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
c.set1(l0);
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// class3: static class task - call via class scope, writes through ref in same always_comb
|
||||
|
||||
class C3;
|
||||
static task automatic set1(ref logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
endclass
|
||||
|
||||
module class3 #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
C3::set1(l0);
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// class4: class composition - one class calls another task, ultimately writes through ref
|
||||
|
||||
class C4Inner;
|
||||
task automatic set1(ref logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
endclass
|
||||
|
||||
class C4Outer;
|
||||
C4Inner inner;
|
||||
function new();
|
||||
inner = new;
|
||||
endfunction
|
||||
task automatic set1(ref logic q);
|
||||
inner.set1(q);
|
||||
endtask
|
||||
endclass
|
||||
|
||||
module class4 #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
C4Outer c;
|
||||
|
||||
initial c = new;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
c.set1(l0);
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// classf0: class function returns value - always_comb writes var directly + via class function call
|
||||
|
||||
class Cf0;
|
||||
function automatic logic ret1();
|
||||
return 1'b1;
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
module classf0 #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
Cf0 c;
|
||||
|
||||
initial c = new;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
l0 = c.ret1();
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// classf1: static class function returns value - always_comb uses class scope call
|
||||
|
||||
class Cf1;
|
||||
static function automatic logic ret1();
|
||||
return 1'b1;
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
module classf1 #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
l0 = Cf1::ret1();
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Shared TB
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel;
|
||||
|
||||
logic val0, val1, val2, val3, val4, valf0, valf1;
|
||||
|
||||
C2 c2;
|
||||
initial c2 = new;
|
||||
|
||||
class0 u0(.sel(sel), .val(val0));
|
||||
class1 u1(.sel(sel), .val(val1));
|
||||
class2 u2(.sel(sel), .val(val2), .c(c2));
|
||||
class3 u3(.sel(sel), .val(val3));
|
||||
class4 u4(.sel(sel), .val(val4));
|
||||
classf0 uf0(.sel(sel), .val(valf0));
|
||||
classf1 uf1(.sel(sel), .val(valf1));
|
||||
|
||||
task automatic check_all(input logic exp);
|
||||
`checkd(val0, exp);
|
||||
`checkd(val1, exp);
|
||||
`checkd(val2, exp);
|
||||
`checkd(val3, exp);
|
||||
`checkd(val4, exp);
|
||||
`checkd(valf0, exp);
|
||||
`checkd(valf1, exp);
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
#1;
|
||||
check_all(1'b0);
|
||||
|
||||
sel = 'b1;
|
||||
#1;
|
||||
check_all(1'b1);
|
||||
|
||||
sel = 'b0;
|
||||
#1;
|
||||
check_all(1'b0);
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// MULTIDRIVEN false positive - package function return var
|
||||
//
|
||||
// Minimal reproducer for: package function with "return expr" used in always_comb expression.
|
||||
// The function return variable must not be treated as a side-effect "writeSummary" target.
|
||||
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
|
||||
package p;
|
||||
function automatic int num_bytes(input int size);
|
||||
return 1 << size;
|
||||
endfunction
|
||||
endpackage
|
||||
|
||||
module t;
|
||||
typedef struct packed {
|
||||
logic [31:0] addr;
|
||||
logic [2:0] size;
|
||||
} meta_t;
|
||||
|
||||
meta_t rd_meta_q;
|
||||
meta_t rd_meta;
|
||||
|
||||
always_comb begin
|
||||
rd_meta = rd_meta_q;
|
||||
rd_meta.addr = rd_meta_q.addr + p::num_bytes(int'(rd_meta_q.size));
|
||||
end
|
||||
|
||||
initial begin
|
||||
rd_meta_q.addr = 32'h100;
|
||||
rd_meta_q.size = 3'd2; // num_bytes = 4
|
||||
#1;
|
||||
`checkd(rd_meta.addr, 32'h104);
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,235 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// Consolidated interface-based multidriven tests
|
||||
// (formerly t_multidriven_iface{0,1,2,3,4,5,6}.v)
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// iface0: direct assignment to interface signal + interface task assign in same process
|
||||
|
||||
interface my_if0;
|
||||
logic l0;
|
||||
task set_l0_1(); l0 = 1'b1; endtask
|
||||
task set_l0_0(); l0 = 1'b0; endtask
|
||||
endinterface
|
||||
|
||||
module iface0 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
my_if0 if0();
|
||||
always_comb begin
|
||||
if0.l0 = 1'b0;
|
||||
if (sel) begin
|
||||
if0.set_l0_1();
|
||||
end
|
||||
end
|
||||
assign val = if0.l0;
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// iface1: interface task chain - nested calls write interface signal in same always_comb
|
||||
|
||||
interface my_if1;
|
||||
logic l0;
|
||||
task set_l0_1_inner(); l0 = 1'b1; endtask
|
||||
task set_l0_1_outer(); set_l0_1_inner(); endtask
|
||||
endinterface
|
||||
|
||||
module iface1 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
my_if1 if0();
|
||||
always_comb begin
|
||||
if0.l0 = 1'b0;
|
||||
if (sel) begin
|
||||
if0.set_l0_1_outer();
|
||||
end
|
||||
end
|
||||
assign val = if0.l0;
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// iface2: interface passed through module port - direct assign + task call in same always_comb
|
||||
|
||||
interface my_if2;
|
||||
logic l0;
|
||||
task set_l0_1(); l0 = 1'b1; endtask
|
||||
task set_l0_0(); l0 = 1'b0; endtask
|
||||
endinterface
|
||||
|
||||
module iface2 #()(
|
||||
input logic sel,
|
||||
output logic val,
|
||||
my_if2 ifp
|
||||
);
|
||||
always_comb begin
|
||||
ifp.l0 = 1'b0;
|
||||
if (sel) begin
|
||||
ifp.set_l0_1();
|
||||
end
|
||||
end
|
||||
assign val = ifp.l0;
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// iface3: interface modport + task import - write interface signal in same always_comb
|
||||
|
||||
interface my_if3;
|
||||
logic l0;
|
||||
task set_l0_1(); l0 = 1'b1; endtask
|
||||
modport mp (
|
||||
output l0,
|
||||
import set_l0_1
|
||||
);
|
||||
endinterface
|
||||
|
||||
module iface3 #()(
|
||||
input logic sel,
|
||||
output logic val,
|
||||
my_if3.mp ifp
|
||||
);
|
||||
always_comb begin
|
||||
ifp.l0 = 1'b0;
|
||||
if (sel) begin
|
||||
ifp.set_l0_1();
|
||||
end
|
||||
end
|
||||
assign val = ifp.l0;
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// iface4: interface task writes through output formal - actual is interface member
|
||||
|
||||
interface my_if4;
|
||||
logic l0;
|
||||
task automatic set_any(output logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
endinterface
|
||||
|
||||
module iface4 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
my_if4 if0();
|
||||
always_comb begin
|
||||
if0.l0 = 1'b0;
|
||||
if (sel) begin
|
||||
if0.set_any(if0.l0);
|
||||
end
|
||||
end
|
||||
assign val = if0.l0;
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// iface5: nested interface test - direct assignment + nested interface task call in same always_comb
|
||||
|
||||
interface leaf_if5;
|
||||
logic l0;
|
||||
task set1(); l0 = 1'b1; endtask
|
||||
endinterface
|
||||
|
||||
interface top_if5;
|
||||
leaf_if5 sub();
|
||||
endinterface
|
||||
|
||||
module iface5 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
top_if5 if0();
|
||||
always_comb begin
|
||||
if0.sub.l0 = 1'b0;
|
||||
if (sel) begin
|
||||
if0.sub.set1();
|
||||
end
|
||||
end
|
||||
assign val = if0.sub.l0;
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// iface6: nested interface aggregator - two nested interfaces, only one driven
|
||||
|
||||
interface chan_if6;
|
||||
logic b0;
|
||||
task set1(); b0 = 1'b1; endtask
|
||||
endinterface
|
||||
|
||||
interface agg_if6;
|
||||
chan_if6 tlb();
|
||||
chan_if6 ic();
|
||||
endinterface
|
||||
|
||||
module iface6 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
agg_if6 a();
|
||||
always_comb begin
|
||||
a.tlb.b0 = 1'b0;
|
||||
if (sel) a.tlb.set1();
|
||||
end
|
||||
assign val = a.tlb.b0;
|
||||
endmodule
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Shared TB
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel;
|
||||
logic val0, val1, val2, val3, val4, val5, val6;
|
||||
|
||||
my_if2 if2();
|
||||
my_if3 if3();
|
||||
|
||||
iface0 u0(.sel(sel), .val(val0));
|
||||
iface1 u1(.sel(sel), .val(val1));
|
||||
iface2 u2(.sel(sel), .val(val2), .ifp(if2));
|
||||
iface3 u3(.sel(sel), .val(val3), .ifp(if3));
|
||||
iface4 u4(.sel(sel), .val(val4));
|
||||
iface5 u5(.sel(sel), .val(val5));
|
||||
iface6 u6(.sel(sel), .val(val6));
|
||||
|
||||
task automatic check_all(input logic exp);
|
||||
`checkd(val0, exp);
|
||||
`checkd(val1, exp);
|
||||
`checkd(val2, exp);
|
||||
`checkd(val3, exp);
|
||||
`checkd(val4, exp);
|
||||
`checkd(val5, exp);
|
||||
`checkd(val6, exp);
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
#1;
|
||||
check_all(1'b0);
|
||||
|
||||
sel = 'b1;
|
||||
#1;
|
||||
check_all(1'b1);
|
||||
|
||||
sel = 'b0;
|
||||
#1;
|
||||
check_all(1'b0);
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
// direct task call
|
||||
module mod0 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
logic l0;
|
||||
task do_stuff();
|
||||
l0 = 'b1;
|
||||
endtask
|
||||
always_comb begin
|
||||
l0 = 'b0;
|
||||
if(sel) begin
|
||||
do_stuff();
|
||||
end
|
||||
end
|
||||
assign val = l0;
|
||||
endmodule
|
||||
|
||||
// nested task call chain
|
||||
module mod1 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
logic l0;
|
||||
task do_inner();
|
||||
l0 = 'b1;
|
||||
endtask
|
||||
task do_outer();
|
||||
do_inner();
|
||||
endtask
|
||||
always_comb begin
|
||||
l0 = 'b0;
|
||||
if (sel) do_outer();
|
||||
end
|
||||
assign val = l0;
|
||||
endmodule
|
||||
|
||||
// task writes through an output arguement
|
||||
module mod2 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
logic l0;
|
||||
task automatic do_stuff(output logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) do_stuff(l0);
|
||||
end
|
||||
assign val = l0;
|
||||
endmodule
|
||||
|
||||
// function call that writes
|
||||
module mod3 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
logic l0;
|
||||
function automatic void do_func();
|
||||
l0 = 1'b1;
|
||||
endfunction
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) do_func();
|
||||
end
|
||||
assign val = l0;
|
||||
endmodule
|
||||
|
||||
// two tasks set0/set1
|
||||
module mod4 #()(
|
||||
input logic sel,
|
||||
output logic val
|
||||
);
|
||||
logic l0;
|
||||
task automatic set1(); l0 = 1'b1; endtask
|
||||
task automatic set0(); l0 = 1'b0; endtask
|
||||
always_comb begin
|
||||
set0();
|
||||
if (sel) begin
|
||||
set1();
|
||||
end
|
||||
end
|
||||
assign val = l0;
|
||||
endmodule
|
||||
|
||||
module m_tb;
|
||||
logic sel;
|
||||
logic v0, v1, v2, v3, v4;
|
||||
|
||||
mod0 u0(.sel(sel), .val(v0));
|
||||
mod1 u1(.sel(sel), .val(v1));
|
||||
mod2 u2(.sel(sel), .val(v2));
|
||||
mod3 u3(.sel(sel), .val(v3));
|
||||
mod4 u4(.sel(sel), .val(v4));
|
||||
|
||||
initial begin
|
||||
#1; sel = 0;
|
||||
`checkd(v0, 0); `checkd(v1, 0); `checkd(v2, 0); `checkd(v3, 0); `checkd(v4, 0);
|
||||
#1; sel = 1;
|
||||
`checkd(v0, 1); `checkd(v1, 1); `checkd(v2, 1); `checkd(v3, 1); `checkd(v4, 1);
|
||||
#1; sel = 0;
|
||||
`checkd(v0, 0); `checkd(v1, 0); `checkd(v2, 0); `checkd(v3, 0); `checkd(v4, 0);
|
||||
#1;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue