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Fix GCC 4.3.2 compile warnings.

This commit is contained in:
Wilson Snyder 2009-04-23 09:16:25 -04:00
parent fb81721e7e
commit cbb3351d97
7 changed files with 23 additions and 21 deletions
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2
Changes
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@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix "cloning" error with -y/--top-module, bug76. [Dimitris Nalbantis] **** Fix "cloning" error with -y/--top-module, bug76. [Dimitris Nalbantis]
**** Fix GCC 4.3.2 compile warnings.
* Verilator 3.702 2009/03/28 * Verilator 3.702 2009/03/28
*** Add --pins-bv option to use sc_bv for all ports. [Brian Small] *** Add --pins-bv option to use sc_bv for all ports. [Brian Small]

2
configure.ac
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@ -72,5 +72,5 @@ AC_SUBST(pkgdatadir)
AC_OUTPUT(Makefile src/Makefile src/Makefile_obj include/verilated.mk) AC_OUTPUT(Makefile src/Makefile src/Makefile_obj include/verilated.mk)
AC_MSG_RESULT([]) AC_MSG_RESULT([])
AC_MSG_RESULT([Now type 'make']) AC_MSG_RESULT([Now type 'gmake'])
AC_MSG_RESULT([]) AC_MSG_RESULT([])

20
include/verilated.h
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@ -336,8 +336,8 @@ static inline void VL_ASSIGNBIT_QI(int, int bit, QData& lhsr, QData rhs) {
} }
static inline void VL_ASSIGNBIT_WI(int, int bit, WDataOutP owp, IData rhs) { static inline void VL_ASSIGNBIT_WI(int, int bit, WDataOutP owp, IData rhs) {
IData orig = owp[VL_BITWORD_I(bit)]; IData orig = owp[VL_BITWORD_I(bit)];
owp[VL_BITWORD_I(bit)] = (orig & ~(VL_UL(1)<<VL_BITBIT_I(bit)) owp[VL_BITWORD_I(bit)] = ((orig & ~(VL_UL(1)<<VL_BITBIT_I(bit)))
| (rhs<<VL_BITBIT_I(bit))); | (rhs<<VL_BITBIT_I(bit)));
} }
// Alternative form that is an instruction faster when rhs is constant one. // Alternative form that is an instruction faster when rhs is constant one.
static inline void VL_ASSIGNBIT_IO(int, int bit, CData& lhsr, IData) { static inline void VL_ASSIGNBIT_IO(int, int bit, CData& lhsr, IData) {
@ -441,7 +441,7 @@ static inline QData VL_EXTENDS_QQ(int, int lbits, QData lhs) {
static inline WDataOutP VL_EXTENDS_WI(int obits, int lbits, WDataOutP owp, IData ld) { static inline WDataOutP VL_EXTENDS_WI(int obits, int lbits, WDataOutP owp, IData ld) {
IData sign = VL_SIGNONES_I(lbits,ld); IData sign = VL_SIGNONES_I(lbits,ld);
owp[0] = ld | sign & ~VL_MASK_I(lbits); owp[0] = ld | (sign & ~VL_MASK_I(lbits));
for (int i=1; i < VL_WORDS_I(obits); i++) owp[i] = sign; for (int i=1; i < VL_WORDS_I(obits); i++) owp[i] = sign;
return(owp); return(owp);
} }
@ -456,7 +456,7 @@ static inline WDataOutP VL_EXTENDS_WW(int obits, int lbits, WDataOutP owp, WData
for (int i=0; i < VL_WORDS_I(lbits)-1; i++) owp[i] = lwp[i]; for (int i=0; i < VL_WORDS_I(lbits)-1; i++) owp[i] = lwp[i];
int lmsw=VL_WORDS_I(lbits)-1; int lmsw=VL_WORDS_I(lbits)-1;
IData sign = VL_SIGNONES_I(lbits,lwp[lmsw]); IData sign = VL_SIGNONES_I(lbits,lwp[lmsw]);
owp[lmsw] = lwp[lmsw] | sign & ~VL_MASK_I(lbits); owp[lmsw] = lwp[lmsw] | (sign & ~VL_MASK_I(lbits));
for (int i=VL_WORDS_I(lbits); i < VL_WORDS_I(obits); i++) owp[i] = sign; for (int i=VL_WORDS_I(lbits); i < VL_WORDS_I(obits); i++) owp[i] = sign;
return(owp); return(owp);
} }
@ -991,16 +991,16 @@ static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int
{ // Lower word { // Lower word
int oword = lword+i; int oword = lword+i;
IData d = lwp[i]<<loffset; IData d = lwp[i]<<loffset;
IData od = owp[oword] & ~linsmask | d & linsmask; IData od = (owp[oword] & ~linsmask) | (d & linsmask);
if (oword==hword) owp[oword] = owp[oword] & ~hinsmask | od & hinsmask; if (oword==hword) owp[oword] = (owp[oword] & ~hinsmask) | (od & hinsmask);
else owp[oword] = od; else owp[oword] = od;
} }
{ // Upper word { // Upper word
int oword = lword+i+1; int oword = lword+i+1;
if (oword <= hword) { if (oword <= hword) {
IData d = lwp[i]>>nbitsonright; IData d = lwp[i]>>nbitsonright;
IData od = d & ~linsmask | owp[oword] & linsmask; IData od = (d & ~linsmask) | (owp[oword] & linsmask);
if (oword==hword) owp[oword] = owp[oword] & ~hinsmask | od & hinsmask; if (oword==hword) owp[oword] = (owp[oword] & ~hinsmask) | (od & hinsmask);
else owp[oword] = od; else owp[oword] = od;
} }
} }
@ -1188,12 +1188,12 @@ static inline IData VL_SHIFTRS_III(int obits, int, int, IData lhs, IData rhs) {
// Note the C standard does not specify the >> operator as a arithmetic shift! // Note the C standard does not specify the >> operator as a arithmetic shift!
IData sign = -(lhs >> (obits-1)); // ffff_ffff if negative IData sign = -(lhs >> (obits-1)); // ffff_ffff if negative
IData signext = ~(VL_MASK_I(obits) >> rhs); // One with bits where we've shifted "past" IData signext = ~(VL_MASK_I(obits) >> rhs); // One with bits where we've shifted "past"
return (lhs >> rhs) | sign & VL_CLEAN_II(obits,obits,signext); return (lhs >> rhs) | (sign & VL_CLEAN_II(obits,obits,signext));
} }
static inline QData VL_SHIFTRS_QQI(int obits, int, int, QData lhs, IData rhs) { static inline QData VL_SHIFTRS_QQI(int obits, int, int, QData lhs, IData rhs) {
QData sign = -(lhs >> (obits-1)); QData sign = -(lhs >> (obits-1));
QData signext = ~(VL_MASK_Q(obits) >> rhs); QData signext = ~(VL_MASK_Q(obits) >> rhs);
return (lhs >> rhs) | sign & VL_CLEAN_QQ(obits,obits,signext); return (lhs >> rhs) | (sign & VL_CLEAN_QQ(obits,obits,signext));
} }
static inline WDataOutP VL_SHIFTRS_WWI(int obits,int,int,WDataOutP owp,WDataInP lwp, IData rd) { static inline WDataOutP VL_SHIFTRS_WWI(int obits,int,int,WDataOutP owp,WDataInP lwp, IData rd) {
int word_shift = VL_BITWORD_I(rd); int word_shift = VL_BITWORD_I(rd);

2
src/V3Const.cpp
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@ -1225,7 +1225,7 @@ private:
AstSenItem* litemp = senp->castSenItem(); AstSenItem* litemp = senp->castSenItem();
AstSenItem* ritemp = cmpp->castSenItem(); AstSenItem* ritemp = cmpp->castSenItem();
if (litemp && ritemp) { if (litemp && ritemp) {
if (litemp->varrefp() && ritemp->varrefp() && litemp->varrefp()->sameTree(ritemp->varrefp()) if ((litemp->varrefp() && ritemp->varrefp() && litemp->varrefp()->sameTree(ritemp->varrefp()))
|| (!litemp->varrefp() && !ritemp->varrefp())) { || (!litemp->varrefp() && !ritemp->varrefp())) {
// We've sorted in the order ANY, BOTH, POS, NEG, so we don't need to try opposite orders // We've sorted in the order ANY, BOTH, POS, NEG, so we don't need to try opposite orders
if (( litemp->edgeType()==AstEdgeType::ANYEDGE) // ANY or {BOTH|POS|NEG} -> ANY if (( litemp->edgeType()==AstEdgeType::ANYEDGE) // ANY or {BOTH|POS|NEG} -> ANY

8
src/V3Inline.cpp
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@ -319,10 +319,10 @@ private:
int refs = nodep->user3(); int refs = nodep->user3();
// Should we automatically inline this module? // Should we automatically inline this module?
// inlineMult = 2000 by default. If a mod*#instances is < this # nodes, can inline it // inlineMult = 2000 by default. If a mod*#instances is < this # nodes, can inline it
bool doit = (userinline || allowed && (refs==1 bool doit = (userinline || (allowed && (refs==1
|| m_stmtCnt < INLINE_MODS_SMALLER || m_stmtCnt < INLINE_MODS_SMALLER
|| v3Global.opt.inlineMult() < 1 || v3Global.opt.inlineMult() < 1
|| refs*m_stmtCnt < v3Global.opt.inlineMult())); || refs*m_stmtCnt < v3Global.opt.inlineMult())));
UINFO(4, " Inline="<<doit<<" Possible="<<allowed<<" Usr="<<userinline<<" Refs="<<refs<<" Stmts="<<m_stmtCnt UINFO(4, " Inline="<<doit<<" Possible="<<allowed<<" Usr="<<userinline<<" Refs="<<refs<<" Stmts="<<m_stmtCnt
<<" "<<nodep<<endl); <<" "<<nodep<<endl);
if (doit) { if (doit) {

8
src/V3Number.cpp
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@ -1063,8 +1063,8 @@ V3Number& V3Number::opMulS (const V3Number& lhs, const V3Number& rhs) {
V3Number lhsNoSign = lhs; if (lhs.isNegative()) lhsNoSign.opUnaryMin(lhs); V3Number lhsNoSign = lhs; if (lhs.isNegative()) lhsNoSign.opUnaryMin(lhs);
V3Number rhsNoSign = rhs; if (rhs.isNegative()) rhsNoSign.opUnaryMin(rhs); V3Number rhsNoSign = rhs; if (rhs.isNegative()) rhsNoSign.opUnaryMin(rhs);
V3Number qNoSign = opMul(lhsNoSign,rhsNoSign); V3Number qNoSign = opMul(lhsNoSign,rhsNoSign);
if (lhs.isNegative() && !rhs.isNegative() if ((lhs.isNegative() && !rhs.isNegative())
|| !lhs.isNegative() && rhs.isNegative()) { || (!lhs.isNegative() && rhs.isNegative())) {
opUnaryMin(qNoSign); opUnaryMin(qNoSign);
} else { } else {
opAssign(qNoSign); opAssign(qNoSign);
@ -1087,8 +1087,8 @@ V3Number& V3Number::opDivS (const V3Number& lhs, const V3Number& rhs) {
V3Number lhsNoSign = lhs; if (lhs.isNegative()) lhsNoSign.opUnaryMin(lhs); V3Number lhsNoSign = lhs; if (lhs.isNegative()) lhsNoSign.opUnaryMin(lhs);
V3Number rhsNoSign = rhs; if (rhs.isNegative()) rhsNoSign.opUnaryMin(rhs); V3Number rhsNoSign = rhs; if (rhs.isNegative()) rhsNoSign.opUnaryMin(rhs);
V3Number qNoSign = opDiv(lhsNoSign,rhsNoSign); V3Number qNoSign = opDiv(lhsNoSign,rhsNoSign);
if (lhs.isNegative() && !rhs.isNegative() if ((lhs.isNegative() && !rhs.isNegative())
|| !lhs.isNegative() && rhs.isNegative()) { || (!lhs.isNegative() && rhs.isNegative())) {
opUnaryMin(qNoSign); opUnaryMin(qNoSign);
} else { } else {
opAssign(qNoSign); opAssign(qNoSign);

2
src/V3Stats.h
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@ -38,7 +38,7 @@ public:
// Implicit conversion operators: // Implicit conversion operators:
inline V3Double0 (const vluint64_t v) : m_d(v) { }; inline V3Double0 (const vluint64_t v) : m_d(v) { };
inline operator const double () const { return m_d; }; inline operator double () const { return m_d; };
// Explicit operators: // Explicit operators:
inline V3Double0& operator++() { ++m_d; return *this; }; // prefix inline V3Double0& operator++() { ++m_d; return *this; }; // prefix