Support module port parameters without defaults, bug 1213.

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>

Changes

@@ -8,6 +8,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ***   Fix ordering of arrayed cell wide connections, bug1202 partial. [Mike Popoloski]
 
+****  Support module port parameters without defaults, bug 1213. [Mike Popoloski]
+
 ****  Fix LITENDIAN warning on arrayed cells, bug1202. [Mike Popoloski]
 
 ****  Fix enum ranges without colons, bug1204. [Mike Popoloski]

src/verilog.y

@@ -2002,6 +2002,8 @@ param_assignment<varp>:		// ==IEEE: param_assignment
 	//			// note exptOrDataType being a data_type is only for yPARAMETER yTYPE
 		id/*new-parameter*/ variable_dimensionListE sigAttrListE '=' exprOrDataType
 	/**/		{ $$ = VARDONEA($<fl>1,*$1, $2, $3); $$->valuep($5); }
+	|	id/*new-parameter*/ variable_dimensionListE sigAttrListE
+	/**/		{ $$ = VARDONEA($<fl>1,*$1, $2, $3); }
 	;
 
 list_of_param_assignments<varp>:	// ==IEEE: list_of_param_assignments

test_regress/t/t_param_default.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+     );
+
+execute (
+     check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_param_default.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003 by Wilson Snyder.
+
+module m #(parameter int Foo);
+endmodule
+
+module t (/*AUTOARG*/);
+
+   m #(10) foo();
+
+   initial begin
+    if (foo.Foo != 10) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+   end
+
+endmodule

test_regress/t/t_param_default_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+     fails=>1,
+     expect=>
+'%Error: Internal Error: t/t_param_default_bad.v:6: ../V3Param.cpp:269: Parameter without initial value
+%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
+.*%Error: Command Failed.*',
+     );
+
+ok(1);
+1;

test_regress/t/t_param_default_bad.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003 by Wilson Snyder.
+
+module m #(parameter int Foo);
+endmodule
+
+module t (/*AUTOARG*/);
+
+   m foo();
+
+endmodule