refine code and Update all four tests and outputs
This commit is contained in:
Yilou Wang
parent
e580eb3bf5
commit
ca2e0cbd8d
|
|
@ -1192,7 +1192,7 @@ VirtIfaceTriggers::makeIfaceToSensMap(AstNetlist* const netlistp, size_t vifTrig
|
|||
VirtIfaceTriggers::IfaceMemberSensMap
|
||||
VirtIfaceTriggers::makeMemberToSensMap(AstNetlist* const netlistp, size_t vifTriggerIndex,
|
||||
AstVarScope* trigVscp) const {
|
||||
std::map<IfaceMember, AstSenTree*> memberToSensMap;
|
||||
IfaceMemberSensMap memberToSensMap;
|
||||
for (const auto& p : m_memberTriggers) {
|
||||
memberToSensMap.emplace(
|
||||
std::make_pair(p.first, createTriggerSenTree(netlistp, trigVscp, vifTriggerIndex)));
|
||||
|
|
|
|||
|
|
@ -186,9 +186,9 @@ public:
|
|||
}
|
||||
|
||||
AstVarScope* findMemberTrigger(const AstIface* ifacep, const std::string& memberName) const {
|
||||
IfaceMember target(ifacep, memberName);
|
||||
IfaceMember target{ifacep, memberName};
|
||||
for (const auto& pair : m_memberTriggers) {
|
||||
if (!(pair.first < target) && !(target < pair.first)) { return pair.second; }
|
||||
if (!(pair.first < target) && !(target < pair.first)) return pair.second;
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@ private:
|
|||
if (!existingTrigger) {
|
||||
AstScope* const scopeTopp = m_netlistp->topScopep()->scopep();
|
||||
// Create a unique name for this member trigger
|
||||
const std::string triggerName = m_vifTriggerNames.get(ifacep) + "__" + memberName;
|
||||
const std::string triggerName = m_vifTriggerNames.get(ifacep) + "_Vtrigm_" + memberName;
|
||||
AstVarScope* const vscp = scopeTopp->createTemp(triggerName, 1);
|
||||
m_triggers.addMemberTrigger(ifacep, memberName, vscp);
|
||||
existingTrigger = vscp;
|
||||
|
|
|
|||
|
|
@ -1,19 +1,12 @@
|
|||
[0] vif1.data==0000
|
||||
[0] intf2.data==0000
|
||||
[0] vif4.data==0000
|
||||
[10] intf2.data==beef
|
||||
[20] vif1.data==dead
|
||||
[20] vif4.data==face
|
||||
[30] intf2.data==beef
|
||||
[40] vif1.data==dead
|
||||
[40] vif4.data==face
|
||||
[50] intf2.data==beef
|
||||
[60] vif1.data==dead
|
||||
[60] vif4.data==face
|
||||
[70] intf2.data==beef
|
||||
[80] intf2.data==beef
|
||||
[80] vif4.data==cafe
|
||||
[90] intf2.data==beef
|
||||
[100] intf2.data==beef
|
||||
[100] vif4.data==deaf
|
||||
[0] vif3.data==0000
|
||||
[0] intf4.data==0000
|
||||
[5000] intf2.data==beef
|
||||
[15000] vif1.data==dead
|
||||
[15000] vif3.data==fafa
|
||||
[15000] intf4.data==face
|
||||
[75000] intf4.data==cafe
|
||||
[95000] vif3.data==cafe
|
||||
[95000] intf4.data==deaf
|
||||
*-* All Finished *-*
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ import vltest_bootstrap
|
|||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["-fno-reorder"])
|
||||
test.compile(verilator_flags2=["--exe --main --timing -fno-reorder"])
|
||||
|
||||
test.execute(expect_filename=test.golden_filename)
|
||||
|
||||
|
|
|
|||
|
|
@ -5,63 +5,69 @@
|
|||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
interface Bus1;
|
||||
logic [15:0] data;
|
||||
logic [15:0] data;
|
||||
endinterface
|
||||
interface Bus2;
|
||||
logic [15:0] data;
|
||||
logic [15:0] data;
|
||||
endinterface
|
||||
interface Bus3;
|
||||
logic [15:0] data;
|
||||
logic [15:0] data;
|
||||
endinterface
|
||||
|
||||
module t (
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
integer cyc = 0;
|
||||
Bus1 intf1();
|
||||
Bus2 intf2();
|
||||
Bus3 intf3(), intf4();
|
||||
virtual Bus1 vif1 = intf1;
|
||||
virtual Bus2 vif2 = intf2;
|
||||
virtual Bus3 vif3 = intf3, vif4 = intf4;
|
||||
module t_controlflow;
|
||||
logic clk = 0;
|
||||
integer cyc = 0;
|
||||
Bus1 intf1();
|
||||
Bus2 intf2();
|
||||
Bus3 intf3(), intf4();
|
||||
virtual Bus1 vif1 = intf1;
|
||||
virtual Bus2 vif2 = intf2;
|
||||
virtual Bus3 vif3 = intf3, vif4 = intf4;
|
||||
|
||||
// Finish on negedge so that $finish is last
|
||||
always @(negedge clk)
|
||||
if (cyc >= 10) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
// Finish on negedge so that $finish is last
|
||||
always @(negedge clk) begin
|
||||
if (cyc >= 10) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
function void assign_to_intf3();
|
||||
if ($c("1")) return;
|
||||
intf3.data = 'hcafe;
|
||||
endfunction
|
||||
function void assign_to_intf3();
|
||||
intf3.data = 'hcafe;
|
||||
endfunction
|
||||
|
||||
always @(posedge clk) begin
|
||||
logic foo = 1;
|
||||
cyc <= cyc + 1;
|
||||
if (cyc == 1 || cyc == 3 || cyc == 5) intf1.data = 'hdead;
|
||||
else vif2.data = 'hbeef;
|
||||
if (cyc == 1 || cyc == 3 || cyc == 5) begin
|
||||
if (cyc >= 3) $c("// dummy statement");
|
||||
else intf3.data = 'hfafa;
|
||||
intf4.data = 'hface;
|
||||
always @(posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc == 1 || cyc == 3 || cyc == 5) intf1.data = 'hdead;
|
||||
else vif2.data = 'hbeef;
|
||||
if (cyc == 1 || cyc == 3 || cyc == 5) begin
|
||||
if (cyc < 3) intf3.data = 'hfafa;
|
||||
intf4.data = 'hface;
|
||||
end
|
||||
if (cyc == 7) begin
|
||||
intf4.data = 'hcafe;
|
||||
end
|
||||
if (cyc == 9) begin
|
||||
assign_to_intf3;
|
||||
intf4.data = 'hdeaf;
|
||||
end
|
||||
end
|
||||
|
||||
always @(vif1.data) begin
|
||||
$write("[%0t] vif1.data==%h\n", $time, vif1.data);
|
||||
end
|
||||
always @(intf2.data) begin
|
||||
$write("[%0t] intf2.data==%h\n", $time, intf2.data);
|
||||
end
|
||||
always @(vif3.data) begin
|
||||
$write("[%0t] vif3.data==%h\n", $time, vif3.data);
|
||||
end
|
||||
always @(intf4.data) begin
|
||||
$write("[%0t] intf4.data==%h\n", $time, intf4.data);
|
||||
end
|
||||
|
||||
initial begin
|
||||
repeat (20) #5ns clk = ~clk;
|
||||
end
|
||||
if (cyc == 7) begin
|
||||
while ($c("0")) begin
|
||||
foo = 0;
|
||||
intf3.data = 'hbebe;
|
||||
end
|
||||
intf4.data = 'hcafe;
|
||||
end
|
||||
if (cyc == 9) begin
|
||||
assign_to_intf3;
|
||||
intf4.data = 'hdeaf;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb $write("[%0t] vif1.data==%h\n", $time, vif1.data);
|
||||
always_comb $write("[%0t] intf2.data==%h\n", $time, intf2.data);
|
||||
always_comb $write("[%0t] vif4.data==%h\n", $time, vif4.data);
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,12 +1,5 @@
|
|||
[0] data==0000
|
||||
[0] data==0000
|
||||
[10] data==0000
|
||||
[20] data==dead
|
||||
[20] data==beef
|
||||
[20] data==beef
|
||||
[30] data==beef
|
||||
[40] data==face
|
||||
[40] data==cafe
|
||||
[40] data==cafe
|
||||
[50] data==cafe
|
||||
*-* All Finished *-*
|
||||
[20000] data==dead
|
||||
[30000] data==beef
|
||||
[40000] data==face
|
||||
[50000] data==cafe
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ import vltest_bootstrap
|
|||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile()
|
||||
test.compile(verilator_flags2=["--exe --main --timing"])
|
||||
|
||||
test.execute(expect_filename=test.golden_filename)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,10 +8,8 @@ interface Bus;
|
|||
logic [15:0] data;
|
||||
endinterface
|
||||
|
||||
module t (
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
module t_sched_act;
|
||||
logic clk = 0;
|
||||
integer cyc = 0;
|
||||
Bus intf();
|
||||
virtual Bus vif = intf;
|
||||
|
|
@ -23,10 +21,10 @@ module t (
|
|||
|
||||
// Finish on negedge so that $finish is last
|
||||
always @(negedge clk)
|
||||
if (cyc >= 5) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
if (cyc >= 6) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
always @(posedge clk or data) begin
|
||||
if (cyc == 1) intf.data <= 'hdead;
|
||||
|
|
@ -35,6 +33,15 @@ module t (
|
|||
else if (cyc == 4) intf.data <= 'hcafe;
|
||||
end
|
||||
|
||||
assign data = vif.data;
|
||||
always_comb $write("[%0t] data==%h\n", $time, data);
|
||||
always @(negedge clk) begin
|
||||
data <= vif.data;
|
||||
end
|
||||
|
||||
always @(data) begin
|
||||
$write("[%0t] data==%h\n", $time, data);
|
||||
end
|
||||
|
||||
initial begin
|
||||
repeat (10) #5ns clk = ~clk;
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,51 +0,0 @@
|
|||
// -*- mode: C++; c-file-style: "cc-mode" -*-
|
||||
//*************************************************************************
|
||||
//
|
||||
// Copyright 2023 by Geza Lore. This program is free software; you can
|
||||
// redistribute it and/or modify it under the terms of either the GNU
|
||||
// Lesser General Public License Version 3 or the Perl Artistic License
|
||||
// Version 2.0.
|
||||
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
//
|
||||
//*************************************************************************
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
#include "Vt_interface_virtual_sched_ico.h"
|
||||
#include "Vt_interface_virtual_sched_ico__Syms.h"
|
||||
|
||||
#include <memory>
|
||||
|
||||
int main(int argc, char** argv) {
|
||||
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
|
||||
contextp->debug(0);
|
||||
contextp->commandArgs(argc, argv);
|
||||
srand48(5);
|
||||
|
||||
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX};
|
||||
topp->clk = false;
|
||||
topp->inc1 = 1;
|
||||
topp->eval();
|
||||
topp->inc2 = 1;
|
||||
topp->eval();
|
||||
|
||||
bool flop = true;
|
||||
while (!contextp->gotFinish() && contextp->time() < 100000) {
|
||||
contextp->timeInc(5);
|
||||
if (topp->clk) {
|
||||
if (flop) {
|
||||
topp->inc1 += 1;
|
||||
} else {
|
||||
topp->inc2 += 1;
|
||||
}
|
||||
flop = !flop;
|
||||
}
|
||||
topp->clk = !topp->clk;
|
||||
topp->eval();
|
||||
}
|
||||
|
||||
if (!contextp->gotFinish()) {
|
||||
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,43 +1,14 @@
|
|||
[0] intf1.inc==0
|
||||
[0] vif2.inc==0
|
||||
[0] intf1.inc==1
|
||||
[0] vif2.inc==0
|
||||
[0] intf1.inc==1
|
||||
[0] vif2.inc==0
|
||||
[0] intf1.inc==1
|
||||
[0] vif2.inc==1
|
||||
[5] intf1.inc==1
|
||||
[5] vif2.inc==1
|
||||
[10] intf1.inc==2
|
||||
[10] vif2.inc==1
|
||||
[15] intf1.inc==2
|
||||
[15] vif2.inc==1
|
||||
[20] intf1.inc==2
|
||||
[20] vif2.inc==2
|
||||
[25] intf1.inc==2
|
||||
[25] vif2.inc==2
|
||||
[30] intf1.inc==3
|
||||
[30] vif2.inc==2
|
||||
[35] intf1.inc==3
|
||||
[35] vif2.inc==2
|
||||
[40] intf1.inc==3
|
||||
[40] vif2.inc==3
|
||||
[45] intf1.inc==3
|
||||
[45] vif2.inc==3
|
||||
[50] intf1.inc==4
|
||||
[50] vif2.inc==3
|
||||
[55] intf1.inc==4
|
||||
[55] vif2.inc==3
|
||||
[60] intf1.inc==4
|
||||
[60] vif2.inc==4
|
||||
[65] intf1.inc==4
|
||||
[65] vif2.inc==4
|
||||
[70] intf1.inc==5
|
||||
[70] vif2.inc==4
|
||||
[75] intf1.inc==5
|
||||
[75] vif2.inc==4
|
||||
[80] intf1.inc==5
|
||||
[80] vif2.inc==5
|
||||
[85] intf1.inc==5
|
||||
[85] vif2.inc==5
|
||||
[0] intf1.inc==00000000
|
||||
[0] vif2.inc==00000001
|
||||
[5000] intf1.inc==00000001
|
||||
[15000] vif2.inc==00000002
|
||||
[15000] intf1.inc==00000002
|
||||
[30000] vif2.inc==00000003
|
||||
[35000] intf1.inc==00000003
|
||||
[45000] vif2.inc==00000004
|
||||
[45000] intf1.inc==00000004
|
||||
[60000] vif2.inc==00000005
|
||||
[65000] intf1.inc==00000005
|
||||
[75000] vif2.inc==00000006
|
||||
[75000] intf1.inc==00000006
|
||||
*-* All Finished *-*
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ import vltest_bootstrap
|
|||
|
||||
test.scenarios('vlt_all')
|
||||
|
||||
test.compile(make_main=False, v_flags2=["--exe", test.pli_filename])
|
||||
test.compile(verilator_flags2=["--exe --main --timing"])
|
||||
|
||||
test.execute(expect_filename=test.golden_filename)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,15 +8,11 @@ interface If;
|
|||
logic [31:0] inc;
|
||||
endinterface
|
||||
|
||||
module top (
|
||||
clk,
|
||||
inc1,
|
||||
inc2
|
||||
);
|
||||
module top;
|
||||
|
||||
input clk;
|
||||
input [31:0] inc1;
|
||||
input [31:0] inc2;
|
||||
logic clk = 0;
|
||||
logic [31:0] inc1 = 0;
|
||||
logic [31:0] inc2 = 0;
|
||||
int cyc = 0;
|
||||
|
||||
If intf1();
|
||||
|
|
@ -24,7 +20,10 @@ module top (
|
|||
virtual If vif1 = intf1;
|
||||
virtual If vif2 = intf2;
|
||||
|
||||
assign vif1.inc = inc1;
|
||||
// assign vif1.inc = inc1;
|
||||
always @(posedge clk) begin
|
||||
vif1.inc <= inc1;
|
||||
end
|
||||
assign intf2.inc = inc2;
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
|
@ -35,7 +34,27 @@ module top (
|
|||
end
|
||||
end
|
||||
|
||||
always_comb $write("[%0t] intf1.inc==%0h\n", $time, intf1.inc);
|
||||
always_comb $write("[%0t] vif2.inc==%0h\n", $time, vif2.inc);
|
||||
always @(intf1.inc) begin
|
||||
$write("[%0t] intf1.inc==%h\n", $time, intf1.inc);
|
||||
end
|
||||
always @(vif2.inc) begin
|
||||
$write("[%0t] vif2.inc==%h\n", $time, vif2.inc);
|
||||
end
|
||||
|
||||
initial begin
|
||||
repeat (30) #5ns clk = ~clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
inc1 = 1;
|
||||
inc2 = 1;
|
||||
|
||||
repeat (10) begin
|
||||
#15ns;
|
||||
inc1 = inc1 + 1;
|
||||
inc2 = inc2 + 1;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,21 +1,10 @@
|
|||
[0] intf1.data==0000
|
||||
[0] intf2.data==0000
|
||||
[0] vif3.data==0000
|
||||
[0] intf2.data==0000
|
||||
[10] intf2.data==0000
|
||||
[10] vif3.data==0000
|
||||
[20] intf1.data==dead
|
||||
[20] intf2.data==0000
|
||||
[20] vif3.data==0000
|
||||
[30] intf2.data==dead
|
||||
[30] vif3.data==0000
|
||||
[40] intf1.data==beef
|
||||
[40] intf2.data==dead
|
||||
[40] vif3.data==0000
|
||||
[50] intf2.data==beef
|
||||
[50] vif3.data==0000
|
||||
[60] intf2.data==beef
|
||||
[60] vif3.data==face
|
||||
[70] intf2.data==beef
|
||||
[70] vif3.data==cafe
|
||||
[15000] intf1.data==dead
|
||||
[30000] intf2.data==dead
|
||||
[35000] intf1.data==beef
|
||||
[50000] intf2.data==beef
|
||||
[55000] vif3.data==face
|
||||
[65000] vif3.data==cafe
|
||||
*-* All Finished *-*
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ import vltest_bootstrap
|
|||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile()
|
||||
test.compile(verilator_flags2=["--exe --main --timing"])
|
||||
|
||||
test.execute(expect_filename=test.golden_filename)
|
||||
|
||||
|
|
|
|||
|
|
@ -16,10 +16,9 @@ interface Bus3;
|
|||
logic [15:0] data;
|
||||
endinterface
|
||||
|
||||
module t (
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
module t;
|
||||
|
||||
logic clk = 0;
|
||||
integer cyc = 0;
|
||||
Bus1 intf1();
|
||||
Bus2 intf2();
|
||||
|
|
@ -29,7 +28,10 @@ module t (
|
|||
virtual Bus3 vif3 = intf3;
|
||||
|
||||
logic [15:0] data;
|
||||
assign vif2.data = data;
|
||||
// assign vif2.data = data;
|
||||
always @(negedge clk) begin
|
||||
vif2.data <= data;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
|
|
@ -54,7 +56,18 @@ module t (
|
|||
$finish;
|
||||
end
|
||||
|
||||
always_comb $write("[%0t] intf1.data==%h\n", $time, intf1.data);
|
||||
always_comb $write("[%0t] intf2.data==%h\n", $time, intf2.data);
|
||||
always_comb $write("[%0t] vif3.data==%h\n", $time, vif3.data);
|
||||
always @(intf1.data) begin
|
||||
$write("[%0t] intf1.data==%h\n", $time, intf1.data);
|
||||
end
|
||||
always @(intf2.data) begin
|
||||
$write("[%0t] intf2.data==%h\n", $time, intf2.data);
|
||||
end
|
||||
always @(vif3.data) begin
|
||||
$write("[%0t] vif3.data==%h\n", $time, vif3.data);
|
||||
end
|
||||
|
||||
initial begin
|
||||
repeat (20) #5ns clk = ~clk;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue