Recognize pragma synthesys to match vhier
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@ -1711,8 +1711,8 @@ assertion clocks.
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=head2 Synthesis Directive Assertion Support
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=head2 Synthesis Directive Assertion Support
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With the --assert switch, Verilator reads any "//synopsys full_case" or "//
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With the --assert switch, Verilator reads any "//synopsys full_case" or "//
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synopsys parallel_case" directives. The same applies to any "//cadence" or
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synopsys parallel_case" directives. The same applies to any "// ambit
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"// ambit synthesis" directives of the same form.
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synthesis", "//cadence" or "//pragma" directives of the same form.
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When these synthesis directives are discovered, Verilator will either
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When these synthesis directives are discovered, Verilator will either
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formally prove the directive to be true, or failing that, will insert the
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formally prove the directive to be true, or failing that, will insert the
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@ -393,6 +393,9 @@ void V3PreProcImp::comment(const string& text) {
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} else if (0==(strncmp(cp,"cadence",strlen("cadence")))) {
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} else if (0==(strncmp(cp,"cadence",strlen("cadence")))) {
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cp+=strlen("cadence");
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cp+=strlen("cadence");
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synth = true;
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synth = true;
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} else if (0==(strncmp(cp,"pragma",strlen("pragma")))) {
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cp+=strlen("pragma");
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synth = true;
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} else if (0==(strncmp(cp,"ambit synthesis",strlen("ambit synthesis")))) {
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} else if (0==(strncmp(cp,"ambit synthesis",strlen("ambit synthesis")))) {
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cp+=strlen("ambit synthesis");
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cp+=strlen("ambit synthesis");
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synth = true;
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synth = true;
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