[#72179] bring back t_trace_counter_saif test with correct SAIF output file

test_regress/t/t_trace_counter.saif

@@ -0,0 +1,27 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "foo")
+(PROGRAM_NAME "Verilator")
+(VERSION "5.032")
+(DIVIDER .)
+(TIMESCALE 1ps)
+(DURATION 1000)
+(INSTANCE foo (NET
+(cyc[0] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
+(cyc[1] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
+(cyc[2] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25))
+(cyc[3] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12))
+(cyc[4] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
+(cyc[5] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3))
+(cyc[6] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1))
+(rst (T0 20) (T1 980) (TZ 0) (TX 0) (TB 0) (TC 3))
+(state[0] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 98))
+(state[1] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 50))
+(state[2] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 24))
+(state[3] (T0 570) (T1 430) (TZ 0) (TX 0) (TB 0) (TC 13))
+(state[4] (T0 600) (T1 400) (TZ 0) (TX 0) (TB 0) (TC 5))
+(state[5] (T0 680) (T1 320) (TZ 0) (TX 0) (TB 0) (TC 2))
+(state[6] (T0 760) (T1 240) (TZ 0) (TX 0) (TB 0) (TC 1))
+(clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
+)))

test_regress/t/t_trace_counter_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test module
+#
+# Copyright 2025 by Antmicro. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_counter.v"
+
+test.compile(verilator_flags2=['--cc --trace-saif'])
+
+test.execute()
+
+#TODO: add function checking if two SAIF files are identical
+#test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()