mirror of
https://github.com/verilator/verilator.git
synced 2026-10-06 10:03:44 +02:00
+17
-3
@@ -38,6 +38,7 @@ class AssertPreVisitor final : public VNVisitor {
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// We're not parsing the tree, or anything more complicated.
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private:
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// NODE STATE
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// AstClockingItem::user1p() // AstVar*. varp() of ClockingItem after unlink
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const VNUser1InUse m_inuser1;
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// STATE
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// Current context:
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@@ -156,19 +157,32 @@ private:
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if (nodep->eventp()) nodep->addNextHere(nodep->eventp()->unlinkFrBack());
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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}
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void visit(AstModportClockingRef* const nodep) override {
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// It has to be converted to a list of ModportClockingVarRefs,
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// because clocking blocks are removed in this pass
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for (AstClockingItem* itemp = nodep->clockingp()->itemsp(); itemp;
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itemp = VN_AS(itemp->nextp(), ClockingItem)) {
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AstVar* const varp = itemp->varp() ? itemp->varp() : VN_AS(itemp->user1p(), Var);
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if (varp) {
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AstModportVarRef* const modVarp
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= new AstModportVarRef{nodep->fileline(), varp->name(), itemp->direction()};
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modVarp->varp(varp);
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nodep->addNextHere(modVarp);
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}
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}
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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}
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void visit(AstClockingItem* const nodep) override {
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// Get a ref to the sampled/driven variable
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AstVar* const varp = nodep->varp();
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if (!varp) {
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// Unused item
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pushDeletep(nodep->unlinkFrBack());
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return;
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}
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FileLine* const flp = nodep->fileline();
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V3Const::constifyEdit(nodep->skewp());
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if (!VN_IS(nodep->skewp(), Const)) {
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nodep->skewp()->v3error("Skew must be constant (IEEE 1800-2023 14.4)");
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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return;
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}
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AstConst* const skewp = VN_AS(nodep->skewp(), Const);
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@@ -176,6 +190,7 @@ private:
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AstNodeExpr* const exprp = nodep->exprp();
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varp->name(m_clockingp->name() + "__DOT__" + varp->name());
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m_clockingp->addNextHere(varp->unlinkFrBack());
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nodep->user1p(varp);
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varp->user1p(nodep);
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if (nodep->direction() == VDirection::OUTPUT) {
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exprp->foreach([](const AstNodeVarRef* varrefp) {
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@@ -292,7 +307,6 @@ private:
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} else {
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nodep->v3fatalSrc("Invalid direction");
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}
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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}
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void visit(AstDelay* nodep) override {
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// Only cycle delays are relevant in this stage; also only process once
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