Fix --coverage on labelled inline assert/cover property (#7898) (#7904)

Fixes #7898

docs/CONTRIBUTORS

@@ -220,6 +220,7 @@ Nikolai Kumar
 Nikolay Puzanov
 Nolan Poe
 Oleh Maksymenko
+Patrick Creighton
 Patrick Stewart
 Paul Bowen-Huggett
 Paul Swirhun

src/V3Coverage.cpp

@@ -385,8 +385,7 @@ class CoverageVisitor final : public VNVisitor {
         VL_RESTORER(m_state);
         VL_RESTORER(m_exprStmtsp);
         VL_RESTORER(m_inToggleOff);
-        // skip properties for expresison coverage
+        m_exprStmtsp = nodep;
-        if (!VN_IS(nodep, Property)) m_exprStmtsp = nodep;
         m_inToggleOff = true;
         createHandle(nodep);
         iterateChildren(nodep);
@@ -745,6 +744,11 @@ class CoverageVisitor final : public VNVisitor {
                 newCoverInc(nodep->fileline(), declp, m_beginHier + "_vlCoverageUserTrace"));
         }
     }
+    void visit(AstPropSpec* nodep) override {
+        VL_RESTORER(m_exprStmtsp);
+        m_exprStmtsp = nullptr;
+        iterateChildren(nodep);
+    }
     void visit(AstStop* nodep) override {
         UINFO(4, "  STOP: " << nodep);
         m_state.m_on = false;

test_regress/t/t_assert_inline_coverage.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--assert --cc --coverage'])
+
+test.execute()
+
+test.passes()

test_regress/t/t_assert_inline_coverage.v

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+    input clk
+);
+
+  integer cyc = 0;
+  logic rst_n = 0;
+  logic en = 0;
+  logic q = 0;
+  logic [7:0] cnt = 0;
+
+  // Synchronous active-low reset driving runtime-varying signals, so the
+  // asserted and covered properties are not constant-folded away.
+  always_ff @(posedge clk) begin
+    rst_n <= (cyc >= 2);
+    en <= cyc[0];
+    if (!rst_n) begin
+      q <= 1'b0;
+      cnt <= '0;
+    end else if (en) begin
+      q <= ~q;
+      cnt <= cnt + 8'd1;
+    end
+  end
+
+  a : assert property (@(posedge clk) !rst_n |=> q == 1'b0);
+
+  c : cover property (@(posedge clk) disable iff (!rst_n) en && cnt == $past(cnt));
+
+  always @(posedge clk) begin
+    cyc <= cyc + 1;
+    if (cyc == 10) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+
+endmodule