Tests: Adding failing test case for source synchronous signals (#3038)

test_regress/t/t_source_sync.out

@@ -0,0 +1,7 @@
+%Error: t/t_source_sync.v:8:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';'
+    8 |    logic clk /*verilator clocker*/ ;
+      |              ^~~~~~~~~~~~~~~~~~~~~
+%Error: t/t_source_sync.v:10:1: syntax error, unexpected '}'
+   10 | } ss_s;
+      | ^
+%Error: Exiting due to

test_regress/t/t_source_sync.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_source_sync.v

@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Dan Petrisko.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef struct packed {
+   logic clk /*verilator clocker*/;
+   logic data;
+} ss_s;
+
+endmodule