Tests: Move most old test_v tests into test_regress.

test_regress/t/t_chg_first.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_chg_first.v

@@ -3,16 +3,13 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_chg (/*AUTOARG*/
+module t (/*AUTOARG*/
-   // Outputs
-   passed,
    // Inputs
    clk, fastclk
    );
 
    input clk;
    input fastclk;	// surefire lint_off_line UDDIXN
-   output passed;  reg passed; initial passed = 0;
 
    integer _mode;  initial _mode=0;
 
@@ -54,8 +51,8 @@ module t_chg (/*AUTOARG*/
       else if (_mode==1) begin
 	 _mode<=2;
 	 if (ord7 !== 7) $stop;
-	 $write("[%0t] t_chg: Passed\n", $time);
+	 $write("*-* All Finished *-*\n");
-	 passed <= 1'b1;
+	 $finish;
       end
    end
 

test_regress/t/t_clk_first.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_first.v

@@ -3,17 +3,39 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_clk (/*AUTOARG*/
+module t (/*AUTOARG*/
-   // Outputs
-   passed,
    // Inputs
-   fastclk, clk, reset_l
+   clk, fastclk
    );
 
-   input fastclk;
+   input clk /*verilator sc_clock*/;
-   input clk;
+   input fastclk /*verilator sc_clock*/;
+   reg 	 reset_l;
+
+   int cyc;
+   initial reset_l = 0;
+   always @ (posedge clk) begin
+      if (cyc==0) reset_l <= 1'b1;
+      else if (cyc==1) reset_l <= 1'b0;
+      else if (cyc==10) reset_l <= 1'b1;
+   end
+
+   t_clk t (/*AUTOINST*/
+	    // Inputs
+	    .clk			(clk),
+	    .fastclk			(fastclk),
+	    .reset_l			(reset_l));
+endmodule
+
+module t_clk (/*AUTOARG*/
+   // Inputs
+   clk, fastclk, reset_l
+   );
+
+   input clk /*verilator sc_clock*/;
+   input fastclk /*verilator sc_clock*/;
    input reset_l;
-   output passed;  reg passed; initial passed = 0;
+
    // surefire lint_off STMINI
    // surefire lint_off CWECSB
    // surefire lint_off NBAJAM
@@ -35,7 +57,9 @@ module t_clk (/*AUTOARG*/
    // verilator lint_on GENCLK
 
    always @ (posedge clk) begin
-      //$write("CLK1 %x\n", reset_l);
+`ifdef TEST_VERBOSE
+      $write("[%0t] CLK1 %x\n", $time, reset_l);
+`endif
       if (!reset_l) begin
 	 clk_clocks <= 0;
 	 int_clocks <= 0;
@@ -46,7 +70,9 @@ module t_clk (/*AUTOARG*/
 	 internal_clk <= ~internal_clk;
 	 if (!_ranit) begin
 	    _ranit <= 1;
+`ifdef TEST_VERBOSE
 	    $write("[%0t] t_clk: Running\n",$time);
+`endif
 	    reset_int_ <= 1;
 	 end
       end
@@ -54,7 +80,9 @@ module t_clk (/*AUTOARG*/
 
    reg [7:0] sig_rst;
    always @ (posedge clk or negedge reset_l) begin
-      //$write("CLK2 %x sr=%x\n", reset_l, sig_rst);
+`ifdef TEST_VERBOSE
+      $write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst);
+`endif
       if (!reset_l) begin
 	 sig_rst <= 0;
       end
@@ -64,7 +92,9 @@ module t_clk (/*AUTOARG*/
    end
 
    always @ (posedge clk) begin
-      //$write("CLK3 %x cc=%x sr=%x\n", reset_l, clk_clocks, sig_rst);
+`ifdef TEST_VERBOSE
+      $write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst);
+`endif
       if (!reset_l) begin
 	 clk_clocks <= 0;
       end
@@ -77,15 +107,17 @@ module t_clk (/*AUTOARG*/
 	    if (int_clocks_copy !== 2) $stop;
 	    if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
 	    if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
-	    passed <= 1'b1;
+	    $write("*-* All Finished *-*\n");
-	    $write("[%0t] t_clk: Passed\n",$time);
+	    $finish;
 	 end
       end
    end
 
    reg [7:0] resetted;
    always @ (posedge clk or negedge reset_int_) begin
-      //$write("CLK4 %x\n", reset_l);
+`ifdef TEST_VERBOSE
+      $write("[%0t] CLK4 %x\n", $time, reset_l);
+`endif
       if (!reset_int_) begin
 	 resetted <= 0;
       end
@@ -112,3 +144,59 @@ module t_clk (/*AUTOARG*/
 		  .reset_l		(reset_l));
 
 endmodule
+
+module t_clk_flop (/*AUTOARG*/
+   // Outputs
+   q, q2,
+   // Inputs
+   clk, clk2, a
+   );
+   parameter WIDTH=8;
+   input clk;
+   input clk2;
+   input [(WIDTH-1):0]  a;
+   output [(WIDTH-1):0] q;
+   output [(WIDTH-1):0] q2;
+   reg [(WIDTH-1):0] q;
+   reg [(WIDTH-1):0] q2;
+   always @ (posedge clk) q<=a;
+   always @ (posedge clk2) q2<=a;
+endmodule
+
+module t_clk_two (/*AUTOARG*/
+   // Inputs
+   fastclk, reset_l
+   );
+   input fastclk;
+   input reset_l;
+   // verilator lint_off GENCLK
+   reg clk2;
+   // verilator lint_on GENCLK
+   reg [31:0] count;
+
+   t_clk_twob tb (.*);
+
+   wire reset_h = ~reset_l;
+   always @ (posedge fastclk) begin
+      if (reset_h) clk2 <= 0;
+      else clk2 <= ~clk2;
+   end
+   always @ (posedge clk2) begin
+      if (reset_h) count <= 0;
+      else count <= count + 1;
+   end
+endmodule
+
+module t_clk_twob (/*AUTOARG*/
+   // Inputs
+   fastclk, reset_l
+   );
+   input fastclk;
+   input reset_l;
+
+   always @ (posedge fastclk) begin
+      // Extra line coverage point, just to make sure coverage
+      // hierarchy under inlining lands properly
+      if (reset_l) ;
+   end
+endmodule

test_regress/t/t_inst_first.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_first.v

@@ -3,23 +3,20 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_inst(/*AUTOARG*/
+module t (/*AUTOARG*/
-   // Outputs
-   passed,
    // Inputs
    clk, fastclk
    );
 
    input clk;
    input fastclk;
-   output passed;  reg passed; initial passed = 0;
 
    genvar unused;
 
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire			o_com;			// From b of t_inst_b.v
+   wire			o_com;			// From b of t_inst_first_b.v
-   wire			o_seq_d1r;		// From b of t_inst_b.v
+   wire			o_seq_d1r;		// From b of t_inst_first_b.v
    // End of automatics
 
    integer _mode;  // initial _mode=0
@@ -50,7 +47,7 @@ module t_inst(/*AUTOARG*/
    wire [168:0] r_wide3 = {ra,rb,rc,rd,rd};
    reg [127:0]	_guard6; initial _guard6=0;
 
-   t_inst_a a (
+   t_inst_first_a a (
 	       .clk		(clk),
 	       // Outputs
 	       .o_w5		({ma,mb,mc,md,me}),
@@ -66,7 +63,8 @@ module t_inst(/*AUTOARG*/
    reg 		i_seq;
    reg		i_com;
    wire [15:14] o2_comhigh;
-   t_inst_b b (
+
+   t_inst_first_b b (
 	       .o2_com			(o2_comhigh),
 	       .i2_com			({i_com,~i_com}),
 	       .wide_for_trace		(128'h1234_5678_aaaa_bbbb_cccc_dddd),
@@ -115,8 +113,8 @@ module t_inst(/*AUTOARG*/
 	 if ({da,db,dc,dd,de} !== 5'b10110) $stop;
 	 if (o_seq_d1r !== ~i_seq) $stop;
 	 //
-	 $write("[%0t] t_inst: Passed\n", $time);
+	 $write("*-* All Finished *-*\n");
-	 passed <= 1'b1;
+	 $finish;
       end
       if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
 	 $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);

test_regress/t/t_inst_first_a.v

@@ -3,7 +3,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_inst_a (/*AUTOARG*/
+module t_inst_first_a (/*AUTOARG*/
    // Outputs
    o_w5, o_w5_d1r, o_w40, o_w104,
    // Inputs

test_regress/t/t_inst_first_b.v

@@ -3,7 +3,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_inst_b (/*AUTOARG*/
+module t_inst_first_b (/*AUTOARG*/
    // Outputs
    o_seq_d1r, o_com, o2_com,
    // Inputs

test_regress/t/t_order_first.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_order_first.v

@@ -3,9 +3,21 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
+module t (/*AUTOARG*/
+   // Inputs
+   fastclk
+   );
+   input fastclk;
+
+   t_netlist tnetlist
+     (.also_fastclk	(fastclk),
+      /*AUTOINST*/
+      // Inputs
+      .fastclk				(fastclk));
+
+endmodule
+
 module t_netlist (/*AUTOARG*/
-   // Outputs
-   passed,
    // Inputs
    fastclk, also_fastclk
    );
@@ -14,7 +26,6 @@ module t_netlist (/*AUTOARG*/
 
    input fastclk;
    input also_fastclk;
-   output passed;  reg passed; initial passed = 0;
    integer _mode; initial _mode = 0;
 
    // This entire module should optimize to nearly nothing...
@@ -42,8 +53,8 @@ module t_netlist (/*AUTOARG*/
       if (_mode==5) begin
 	 if (a2 != 5'd2) $stop;
 	 if (e != 5'd5) $stop;
-	 $write("[%0t] t_netlist: Passed\n",$time);
+	 $write("*-* All Finished *-*\n");
-	 passed <= 1'd1;
+	 $finish;
       end
       _mode <= _mode + 1;
    end

test_regress/t/t_param_first.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_param_first.v

@@ -3,29 +3,26 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_param(/*AUTOARG*/
+module t(/*AUTOARG*/
-   // Outputs
-   passed,
    // Inputs
    clk
    );
 
    input clk;
-   output passed;  reg passed; initial passed = 0;
    reg 	 _ranit;
 
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire [4:0]		par1;			// From a1 of t_param_a.v
+   wire [4:0]		par1;			// From a1 of t_param_first_a.v
-   wire [4:0]		par2;			// From a2 of t_param_a.v
+   wire [4:0]		par2;			// From a2 of t_param_first_a.v
-   wire [4:0]		par3;			// From a3 of t_param_a.v
+   wire [4:0]		par3;			// From a3 of t_param_first_a.v
-   wire [4:0]		par4;			// From a4 of t_param_a.v
+   wire [4:0]		par4;			// From a4 of t_param_first_a.v
-   wire [1:0]		varwidth1;		// From a1 of t_param_a.v
+   wire [1:0]		varwidth1;		// From a1 of t_param_first_a.v
-   wire [2:0]		varwidth2;		// From a2 of t_param_a.v
+   wire [2:0]		varwidth2;		// From a2 of t_param_first_a.v
-   wire [3:0]		varwidth3;		// From a3 of t_param_a.v
+   wire [3:0]		varwidth3;		// From a3 of t_param_first_a.v
-   wire [3:0]		varwidth4;		// From a4 of t_param_a.v
+   wire [3:0]		varwidth4;		// From a4 of t_param_first_a.v
    // End of automatics
-   /*t_param_a AUTO_TEMPLATE (
+   /*t_param_first_a AUTO_TEMPLATE (
 		      .par		(par@[]));
 		      .varwidth		(varwidth@[]));
     */
@@ -34,25 +31,29 @@ module t_param(/*AUTOARG*/
 
    parameter THREE = 3;
 
-   t_param_a #(1,5) a1 (
+   t_param_first_a #(1,5) a1
+     (
       // Outputs
       .varwidth		(varwidth1[1:0]),
       /*AUTOINST*/
       // Outputs
       .par				(par1[4:0]));		 // Templated
-   t_param_a #(2,5) a2 (
+   t_param_first_a #(2,5) a2
+     (
       // Outputs
       .varwidth		(varwidth2[2:0]),
       /*AUTOINST*/
       // Outputs
       .par				(par2[4:0]));		 // Templated
-   t_param_a #(THREE,5) a3 (
+   t_param_first_a #(THREE,5) a3
+     (
       // Outputs
       .varwidth		(varwidth3[3:0]),
       /*AUTOINST*/
       // Outputs
       .par				(par3[4:0]));		 // Templated
-   t_param_a #(THREE,5) a4 (
+   t_param_first_a #(THREE,5) a4
+     (
       // Outputs
       .varwidth		(varwidth4[3:0]),
       /*AUTOINST*/
@@ -137,8 +138,8 @@ module t_param(/*AUTOARG*/
 	 // surefire lint_on ASWCMB
 	 // surefire lint_on ASWCBB
 	 //
-	 $write("[%0t] t_param: Passed\n", $time);
+	 $write("*-* All Finished *-*\n");
-	 passed <= 1'b1;
+	 $finish;
       end
    end
 

test_regress/t/t_param_first_a.v

@@ -3,7 +3,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_param_a (/*AUTOARG*/
+module t_param_first_a (/*AUTOARG*/
    // Outputs
    varwidth, par
    );
@@ -14,11 +14,12 @@ module t_param_a (/*AUTOARG*/
 
    /*AUTOOUTPUT*/
    // Beginning of automatic outputs (from unused autoinst outputs)
-   output [4:0]		par;			// From b of t_param_b.v
+   output [4:0]		par;			// From b of t_param_first_b.v
-   output [X:0]		varwidth;		// From b of t_param_b.v
+   output [X:0]		varwidth;		// From b of t_param_first_b.v
    // End of automatics
 
-   t_param_b #(X,FIVE,TWO) b (/*AUTOINST*/
+   t_param_first_b #(X,FIVE,TWO) b
+     (/*AUTOINST*/
       // Outputs
       .par				(par[4:0]),
       .varwidth				(varwidth[X:0]));

test_regress/t/t_param_first_b.v

@@ -3,7 +3,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2003 by Wilson Snyder.
 
-module t_param_b (/*AUTOARG*/
+module t_param_first_b (/*AUTOARG*/
    // Outputs
    par, varwidth
    );

test_v/t.v

@@ -15,57 +15,31 @@ module t (/*AUTOARG*/
    input reset_l;
    output passed;
 
-   // Combine passed signals from each sub signal
+   reg [31:0] count_c;
-   // verilator lint_off MULTIDRIVEN
+   reg [31:0] count_f;
-   wire [20:0] passedv;
-   // verilator lint_on MULTIDRIVEN
-   wire   passed = &passedv;
 
-   assign passedv[0] = 1'b1;
+   always @ (posedge clk) begin
-   assign passedv[1] = 1'b1;
+      if (!reset_l) begin
-   assign passedv[2] = 1'b1;
+	 /*AUTORESET*/
-   assign passedv[3] = 1'b1;
+	 // Beginning of autoreset for uninitialized flops
-   assign passedv[4] = 1'b1;
+	 count_c <= 32'h0;
-   assign passedv[5] = 1'b1;
+	 // End of automatics
-   t_inst  tinst
+      end else begin
-     (.passed		(passedv[6]),
+	 count_c <= count_c + 1;
-      /*AUTOINST*/
+      end
-      // Inputs
+   end
-      .clk				(clk),
+
-      .fastclk				(fastclk));
+   always @ (posedge fastclk) begin
-   t_param tparam
+      if (!reset_l) begin
-     (.passed		(passedv[7]),
+	 /*AUTORESET*/
-      /*AUTOINST*/
+	 // Beginning of autoreset for uninitialized flops
-      // Inputs
+	 count_f <= 32'h0;
-      .clk				(clk));
+	 passed <= 1'h0;
-   assign passedv[8] = 1'b1;
+	 // End of automatics
-   assign passedv[9] = 1'b1;
+      end else begin
-   assign passedv[10] = 1'b1;
+	 count_f <= count_f + 1;
-   t_clk tclk
+	 if (count_f == 5) passed <= 1'b1;
-     (.passed		(passedv[11]),
+      end
-      /*AUTOINST*/
+   end
-      // Inputs
-      .fastclk				(fastclk),
-      .clk				(clk),
-      .reset_l				(reset_l));
-   assign passedv[12] = 1'b1;
-   assign passedv[13] = 1'b1;
-   t_chg tchg
-     (.passed		(passedv[14]),
-      /*AUTOINST*/
-      // Inputs
-      .clk				(clk),
-      .fastclk				(fastclk));
-   assign passedv[15] = 1'b1;
-   assign passedv[16] = 1'b1;
-   assign passedv[17] = 1'b1;
-   assign passedv[18] = 1'b1;
-   assign passedv[19] = 1'b1;
-   t_netlist tnetlist
-     (.passed		(passedv[20]),
-      .also_fastclk	(fastclk),
-      /*AUTOINST*/
-      // Inputs
-      .fastclk				(fastclk));
 
 endmodule

test_v/t_clk_flop.v

@@ -1,24 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
-
-`include "verilated.v"
-
-module t_clk_flop (/*AUTOARG*/
-   // Outputs
-   q, q2,
-   // Inputs
-   clk, clk2, a
-   );
-   parameter WIDTH=8;
-   input clk;
-   input clk2;
-   input [(WIDTH-1):0]  a;
-   output [(WIDTH-1):0] q;
-   output [(WIDTH-1):0] q2;
-   reg [(WIDTH-1):0] q;
-   reg [(WIDTH-1):0] q2;
-   always @ (posedge clk) q<=a;
-   always @ (posedge clk2) q2<=a;
-endmodule

test_v/t_clk_two.v

@@ -1,44 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2003 by Wilson Snyder.
-
-`include "verilated.v"
-
-module t_clk_two (/*AUTOARG*/
-   // Inputs
-   fastclk, reset_l
-   );
-   input fastclk;
-   input reset_l;
-   // verilator lint_off GENCLK
-   reg clk2;
-   // verilator lint_on GENCLK
-   reg [31:0] count;
-
-   t_clk_twob tb (.*);
-
-   wire reset_h = ~reset_l;
-   always @ (posedge fastclk) begin
-      if (reset_h) clk2 <= 0;
-      else clk2 <= ~clk2;
-   end
-   always @ (posedge clk2) begin
-      if (reset_h) count <= 0;
-      else count <= count + 1;
-   end
-endmodule
-
-module t_clk_twob (/*AUTOARG*/
-   // Inputs
-   fastclk, reset_l
-   );
-   input fastclk;
-   input reset_l;
-
-   always @ (posedge fastclk) begin
-      // Extra line coverage point, just to make sure coverage
-      // hierarchy under inlining lands properly
-      if (reset_l) ;
-   end
-endmodule

test_v/top.v

@@ -28,7 +28,11 @@ module top (/*AUTOARG*/
    wire [39:0] 	 out_quad = in_quad | {40{reset_l}};
    wire [69:0] 	 out_wide = in_wide | {70{reset_l}};
 
-   // Test cases
+   initial begin
+      $write("Hello World!\n");
+   end
+
+   // Example sub module
    t t (/*AUTOINST*/
 	// Outputs
 	.passed				(passed),