Tests: Fix commentary to unify issue references.

src/V3AstNodes.cpp

@@ -2317,7 +2317,7 @@ void AstCAwait::dump(std::ostream& str) const {
 int AstCMethodHard::instrCount() const {
     if (AstBasicDType* const basicp = fromp()->dtypep()->basicp()) {
         // TODO: add a more structured description of library methods, rather than using string
-        //       matching. See #3715.
+        //       matching. See issue #3715.
         if (basicp->isTriggerVec() && m_name == "word") {
             // This is an important special case for scheduling so we compute it precisely,
             // it is simply a load.

src/V3Global.h

@@ -102,7 +102,7 @@ class V3Global final {
     bool m_assertDTypesResolved = false;  // Tree should have dtypep()'s
     bool m_assertScoped = false;  // Tree is scoped
     bool m_constRemoveXs = false;  // Const needs to strip any Xs
-    // Experimenting with always requiring heavy, see (#2701)
+    // Experimenting with always requiring heavy, see issue #2701
     bool m_needTraceDumper = false;  // Need __Vm_dumperp in symbols
     bool m_dpi = false;  // Need __Dpi include files
     bool m_hasEvents = false;  // Design uses SystemVerilog named events

src/V3Partition.cpp

@@ -1974,7 +1974,7 @@ private:
         }
         // Not: Find all reader tasks for this variable, group by rank.
         // There was "broken" code here to find readers, but fixing it to
-        // work properly harmed performance on some tests, see #3360.
+        // work properly harmed performance on some tests, see issue #3360.
     }
     void mergeSameRankTasks(const TasksByRank& tasksByRank) {
         LogicMTask* lastRecipientp = nullptr;

test_regress/t/t_bitsel_const_bad.v

@@ -1,6 +1,6 @@
 // DESCRIPTION: Verilator: Test of select from constant
 //
-// This tests issue 508, bit select of constant fails
+// This tests issue #508, bit select of constant fails
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2012 by Jeremy Bennett.

test_regress/t/t_bitsel_wire_array_bad.v

@@ -1,6 +1,6 @@
 // DESCRIPTION: Verilator: Test of select from constant
 //
-// This tests issue 509, bit select of constant fails
+// This tests issue #509, bit select of constant fails
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2012 by Jeremy Bennett.

test_regress/t/t_clk_inp_init.v

@@ -1,6 +1,6 @@
 // DESCRIPTION: Verilator: Check initialisation of cloned clock variables
 //
-// This tests issue 1327 (Strange initialisation behaviour with
+// This tests issue #1327 (Strange initialisation behaviour with
 // "VinpClk" cloned clock variables)
 //
 // This file ONLY is placed into the Public Domain, for any use,

test_regress/t/t_const_opt.v

@@ -166,14 +166,14 @@ module bug3197(input wire clk, input wire [31:0] in, output out);
 endmodule
 
 
-// Bug #3445
+// See issue #3445
 // An unoptimized node is kept as frozen node, but its LSB and polarity were not saved.
 // AST of RHS of result0 looks as below:
 //   AND(SHIFTR(AND(WORDSEL(ARRAYSEL(VARREF)), WORDSEL(ARRAYSEL(VARREF)))), 32'd11)
 //                  ~~~~~~~~~~~~~~~~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~
 // Two of WORDSELs are frozen nodes. They are under SHIFTR of 11 bits.
 //
-// Fixing #3445 needs to
+// Fixing issue #3445 needs to
 //  1. Take AstShiftR and AstNot into op count when diciding optimizable or not
 //     (result0 and result2 in the test)
 //  2. Insert AstShiftR if LSB of the frozen node is not 0 (result1 in the test)
@@ -368,10 +368,10 @@ module bug3824(input wire clk, input wire [31:0] in, output wire out);
   assign out = d_and ^ d_or ^ d_xor;
 endmodule
 
-/// Bug4059
+/// See issue #4059
 // Frozen node in an xor tree held unnecessary poloarity.
 // In an XOR tree, the entire result is flipped if necessary according to
-// total polarity. This bug was introduced when fixing #3445.
+// total polarity. This bug was introduced when fixing issue #3445.
 module bug4059(input wire clk, input wire [31:0] in, output wire out);
    wire [127:0] words_i;
    for (genvar i = 0; i < $bits(in); ++i) begin

test_regress/t/t_const_slicesel.v

@@ -13,7 +13,7 @@ localparam int unsigned A3 [2:0] = '{4,5,6};
 localparam int unsigned B22 [1:0] = A2[1:0];
 localparam int unsigned B33 [2:0] = A3[2:0];
 
-// bug #3186
+// See issue #3186
 localparam int unsigned B32_B [1:0] = A3[1:0];
 localparam int unsigned B32_T [1:0] = A3[2:1];
 

test_regress/t/t_delay.v

@@ -42,7 +42,7 @@ module t (/*AUTOARG*/
       else if (cyc == 4) begin
          dly_s.dly = 55;
          dly0 <= #(dly_s.dly) 32'h55;
-         //dly0 <= # dly_s.dly 32'h55;  // Unsupported, issue-2410
+         //dly0 <= # dly_s.dly 32'h55;  // Unsupported, issue #2410
       end
       else if (cyc == 99) begin
          if (dly3 !== 32'h57) $stop;

test_regress/t/t_fork_initial.pl

@@ -13,11 +13,11 @@ scenarios(simulator => 1);
 compile(
     verilator_flags2 => ["--exe --main --timing"],
     make_main => 0,
-    # bug#4471 - remove this
+    # issue #4471 - remove this
     verilator_make_gmake => 0,
     );
 
-#bug#4471 - add this
+# issue #4471 - add this
 #execute(
 #    check_finished => 1,
 #    );

test_regress/t/t_gen_index.v

@@ -3,7 +3,7 @@
 // The code illustrates a problem in Verilator's handling of constant
 // expressions inside generate indexes.
 //
-// This is a regression test against issue 517.
+// This is a regression test against issue #517.
 //
 // **If you do not wish for your code to be released to the public
 // please note it here, otherwise:**

test_regress/t/t_lint_latch_1.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
+// DESCRIPTION: Verilator: Verilog Test module for issue #1609
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2020 by Julien Margetts.

test_regress/t/t_lint_latch_2.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
+// DESCRIPTION: Verilator: Verilog Test module for issue #1609
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2020 by Julien Margetts.

test_regress/t/t_lint_latch_3.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
+// DESCRIPTION: Verilator: Verilog Test module for issue #1609
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2020 by Julien Margetts.

test_regress/t/t_lint_latch_4.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#2938
+// DESCRIPTION: Verilator: Verilog Test module for issue #2938
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2021 by Julien Margetts (Originally provided by YanJiun)

test_regress/t/t_lint_latch_5.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#2863
+// DESCRIPTION: Verilator: Verilog Test module for issue #2863
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2021 by Julien Margetts (Originally provided by Thomas Sailer)

test_regress/t/t_lint_latch_6.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#221
+// DESCRIPTION: Verilator: Verilog Test module for issue #221
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2023 by Julien Margetts (Originally provided by Adrien Le Masle)

test_regress/t/t_lint_latch_bad_2.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
+// DESCRIPTION: Verilator: Verilog Test module for issue #1609
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2020 by Julien Margetts.

test_regress/t/t_lint_latch_bad_3.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
+// DESCRIPTION: Verilator: Verilog Test module for issue #1609
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2020 by Julien Margetts.

test_regress/t/t_lint_nolatch_bad.v

@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
+// DESCRIPTION: Verilator: Verilog Test module for issue #1609
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2020 by Julien Margetts.

test_regress/t/t_merge_cond_bug_3409.v

@@ -82,7 +82,7 @@ module Test(/*AUTOARG*/
       integer x;
       row_idx = {2{1'b0}};
       row_found = 1'b0;
-      // Bug #3409: After unrolling, these conditionals should not be merged
+      // Issue #3409: After unrolling, these conditionals should not be merged
       // as row_found is assigned.
       for (x = 0; $unsigned(x) < 4; x = x + 1) begin
          row_idx = !row_found ? x[1:0] : row_idx;

test_regress/t/t_mod_nomod.v

@@ -4,7 +4,7 @@
 // any use, without warranty, 2019 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-//bug 1381
+// See issue #1381
 
 logic root_var;
 

test_regress/t/t_order_loop_bad.v

@@ -4,7 +4,7 @@
 // the use of ready in the first two always blocks. However it should
 // trivially trigger the $write on the first clk posedge.
 //
-// This is a regression test against issue 513.
+// This is a regression test against issue #513.
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2012 by Jeremy Bennett.

test_regress/t/t_order_quad.v

@@ -4,7 +4,7 @@
 // any use, without warranty, 2014 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-//bug 762
+// See issue #762
 module t(a0, y);
    input [3:0] a0;
    output [44:0] y;

test_regress/t/t_package_ddecl.v

@@ -4,7 +4,7 @@
 // any use, without warranty, 2012 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-// see bug 474
+// See issue #474
 package functions;
    localparam LP_PACK = 512;
    localparam LP_PACK_AND_MOD = 19;

test_regress/t/t_package_export.v

@@ -4,7 +4,7 @@
 // without warranty, 2012 by Jeremy Bennett.
 // SPDX-License-Identifier: CC0-1.0
 
-// see bug 591
+// See issue #591
 
 package pkg1;
    parameter PARAM2 = 16;

test_regress/t/t_package_twodeep.v

@@ -4,7 +4,7 @@
 // without warranty, 2012 by Jeremy Bennett
 // SPDX-License-Identifier: CC0-1.0
 
-// see bug 591
+// See issue #591
 
 package pkg2;
    parameter PARAM2 = 16;

test_regress/t/t_param.v

@@ -48,7 +48,7 @@ module m1;
    initial if (PACKED_PARAM != 8'h36) $stop;
 endmodule
 
-// bug 810
+// See issue #810
 module m2 #(/*parameter*/ integer PAR2 = 10);
    initial begin
       $display("%x",PAR2);

test_regress/t/t_param_wide_io.v

@@ -4,7 +4,7 @@
 // any use, without warranty, 2016 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-// issue 1991
+// See issue #1991
 
 module t
   #(

test_regress/t/t_param_width.v

@@ -4,7 +4,7 @@
 // any use, without warranty, 2016 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-// issue 1991
+// See issue #1991
 
 module t
   (/*AUTOARG*/

test_regress/t/t_randcase_bad.v

@@ -1,6 +1,6 @@
 // DESCRIPTION: Verilator: Test of select from constant
 //
-// This tests issue 508, bit select of constant fails
+// This tests issue #508, bit select of constant fails
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2022 by Wilson Snyder.

test_regress/t/t_struct_unaligned.v

@@ -1,6 +1,6 @@
 // DESCRIPTION: Verilator:
 //  Test an error where a shift amount was out of bounds and the compiler treats the
-//  value as undefined (Issue #803)
+//  value as undefined (issue #803)
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2014 by Jeff Bush.

test_regress/t/t_sys_plusargs.v

@@ -50,17 +50,17 @@ module t;
       if (!$value$plusargs("INT=%o", p_i)) $stop;
       if (p_i !== 32'o1234) $stop;
 
-      // Check handling of 'SData' type signals (Issue #1592)
+      // Check handling of 'SData' type signals (issue #1592)
       p_s = 0;
       if (!$value$plusargs("INT=%d", p_s)) $stop;
       if (p_s !== 16'd1234) $stop;
 
-      // Check handling of 'CData' type signals (Issue #1592)
+      // Check handling of 'CData' type signals (issue #1592)
       p_c = 0;
       if (!$value$plusargs("INT=%d", p_c)) $stop;
       if (p_c !== 8'd210) $stop;
 
-      // Check handling of 'double' type signals (Issue #1619)
+      // Check handling of 'double' type signals (issue #1619)
       p_r = 0;
       if (!$value$plusargs("REAL=%e", p_r)) $stop;
       $display("r='%e'", p_r);

test_regress/t/t_tri_select_unsized.v

@@ -14,12 +14,12 @@ module t (/*AUTOARG*/
 
    wire [1:0]  b;
    wire [1:0]  c;
-   wire [0:0]  d;  // Explicit width due to issue 508
+   wire [0:0]  d;  // Explicit width due to issue #508
    wire [0:0]  e;
 
    // This works if we use 1'bz, or 1'bx, but not with just 'bz or 'bx. It
    // does require the tri-state Z. Since we get the same effect if b is
-   // dimensioned [0:0], this may be connected to issue 508.
+   // dimensioned [0:0], this may be connected to issue #508.
    assign b[1:0] = clk ? 2'bx : 'bz;
    assign c[1:0] = clk ? 2'bz : 'bx;
    assign d      = clk ? 1'bx : 'bz;

test_regress/t/t_vpi_get.cpp

@@ -121,7 +121,7 @@ static int _mon_check_props(TestVpiHandle& handle, int size, int direction, int
         // check direction of object
         int vpidir = vpi_get(vpiDirection, handle);
         // Don't check port directions in verilator
-        // see #681
+        // See issue #681
         if (!TestSimulator::is_verilator()) CHECK_RESULT(vpidir, direction);
     }
 
@@ -129,7 +129,7 @@ static int _mon_check_props(TestVpiHandle& handle, int size, int direction, int
     int vpitype = vpi_get(vpiType, handle);
     if (!(TestSimulator::is_verilator() && type == vpiPort)) {
         // Don't check for ports in verilator
-        // see #681
+        // See issue #681
         CHECK_RESULT(vpitype, type);
     }